DLA MIL-HDBK-62 CHG NOTICE 1-2002 DOCUMENTATION OF DIGITAL ELECTRONIC SYSTEMS WITH VHDL《VHDL数字电子系统文件》.pdf

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1、 METRICMIL-HDBK-6213 September 1996DEPARTMENT OF DEFENSEHANDBOOKDOCUMENTATION OF DIGITALELECTRONIC SYSTEMS WITH VHDLThis handbook is for guidance only.Do not cite this document as a requirement.AMSC/NA FSC 5962DISTRIBUTION STATEMENT A. Approved for public release; distribution isunlimited.Thi d t t

2、d ith F M k 4 0 4Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-HDBK-62 NOTICE 1 26 September 2002 DEPARTMENT OF DEFENSE HANDBOOK DOCUMENTATION OF DIGITAL ELECTRONIC SYSTEMS WITH VHDL TO ALL HOLDERS OF MIL-HDBK-62: 1. THE FOLLOWING PAGES OF MIL-

3、HDBK-62 HAVE BEEN REVISED AND SUPERSEDE THE PAGES LISTED: NEW PAGE DATE SUPERSEDED PAGE DATE 1-4 26 September 2002 1-4 13 September 1996 1-5 13 September 1996 1-5 Reprinted without change 2-13 26 September 2002 2-13 13 September 1996 2-14 13 September 1996 2-14 Reprinted without change 2-23 13 Septe

4、mber 1996 2-23 Reprinted without change 2-24 26 September 2002 2-24 13 September 1996 3-25 13 September 1996 3-25 Reprinted without change 4-1 26 September 2002 4-1 13 September 1996 4-2 26 September 2002 4-2 13 September 1996 4-3 13 September 1996 4-3 Reprinted without change 4-8 26 September 2002

5、4-8 13 September 1996 4-9 26 September 2002 4-9 13 September 1996 G-5 26 September 2002 G-5 13 September 1996 G-6 13 September 1996 G-6 Reprinted without change ST-1 26 September 2002 ST-1 13 September 1996 2. RETAIN THIS NOTICE AND INSERT BEFORE TABLE OF CONTENTS. 3. Holders of MIL-HDBK-62 will ver

6、ify that page changes and additions indicated above have been entered. This notice page will be retained as a check sheet. This issuance, together with appended pages, is a separate publication. Each notice is to be retained by stocking points until the standard is completely revised or canceled. Cu

7、stodians: Preparing activity: Army - CR DLA CC Navy - EC Air Force - 11 DLA - DH Review activity: (Project 5962-1932) Air Force 19 AMSC N/A FSC 5962 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. NOTICE OF CHANGE METRIC Provided by IHSNot for ResaleNo reproduction

8、or networking permitted without license from IHS-,-,-MIL-HDBK-62iiFOREWORD1. This handbook is approved for use by all Departments and Agencies of the Department of Defense (DoD).2. This handbook is for guidance only. This handbook cannot be cited as a requirement. If it is, the contractordoes not ha

9、ve to comply.3. This handbook was developed to provide guidance to Department of Defense personnel who are writing re-quests for proposals for military digital electronic systems, DoD contractors who are developing very high-speedintegrated circuit (VHSIC) hardware description language (VHDL) models

10、 for the Government, and DoD engi-neers, scientists, and management or independent validation and verification contractors who are evaluating or re-viewing models delivered to the Government. It documents the state of the art and existing technologies for VHDLmodel development. Addressed in the hand

11、book are which VHDL models are required to be delivered with a con-tract, which VHDL models should be developed during the different stages of the lifetime of a system, and howVHDL models can be structured to be consistent with modeling standards.4. This handbook was developed under the auspices of

12、the US Army Materiel Commands Engineering DesignHandbook Program, which is under the direction of the US Army Industrial Engineering Activity. Research TriangleInstitute (RTI) was the prime contractor for this handbook under Contract No. DAAA09-86-D-0009. The handbookwas authored by Dr. Geoffrey A.

13、Frank and edited by Ray C. Anderson of RTI. Development of this handbook wasguided by a technical working group that included Mr. Gerald T. Michael, US Army Research Laboratory, chair-man; Dr. John W. Hines, US Air Force Wright Laboratory; Mr. J. P. Letellier, US Naval Research Laboratory; andMr. Mi

14、chael A. Frye, US Department of Defense, Defense Logistics Agency.5. Beneficial comments (recommendations, additions, deletions) and any pertinent data that may be of use in im-proving this document should be addressed to Defense Supply Center Columbus, ATTN: Director-VA, 3990 EastBroad Street, Colu

15、mbus, OH 43216-5000, by using the Standardization Document Improvement Proposal (DDForm 1426) appearing at the end of this document or by letter.The following is included at the request of IEEE:“The Institute of Electrical and Electronics Engineers, Inc. (IEEE) disclaims any responsibility or liabil

16、ity resulting fromthe placement and use in this publication of material extracted from its publications. Information is reprinted with permissionof the IEEE.”Thi d t t d ith F M k 4 0 4Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-iiiMIL-HDBK-62CON

17、TENTSFOREWORD .iiLIST OF ILLUSTRATIONS ixLIST OF TABLES xiLIST OF ABBREVIATIONS AND ACRONYMS.xiiCHAPTER 1INTRODUCTION1-1 PURPOSE . 1-11-2 SCOPE 1-11-3 INTENDED AUDIENCE . 1-11-4 HISTORY, PURPOSE, AND SCOPE OF VHDL . 1-21-4.1 HISTORY OF VHDL . 1-21-4.2 THE PURPOSE OF VHDL 1-21-4.3 THE SCOPE OF VHDL 1

18、-31-5 RELATED INDUSTRY STANDARDS 1-31-6 OVERVIEW . 1-3REFERENCES . 1-4BIBLIOGRAPHY 1-5CHAPTER 2 HARDWARE DESCRIPTION CONCEPTS2-1 INTRODUCTION 2-12-2 LEVELS OF ABSTRACTION IN MODELS OF DIGITAL ELECTRONIC SYSTEMS 2-22-2.1 OVERVIEW 2-22-2.2 NETWORK MODELS 2-32-2.2.1 Performance Models . 2-32-2.2.2 Inte

19、rface models . 2-32-2.3 ALGORITHMIC MODELS 2-42-2.4 INSTRUCTION SET ARCHITECTURE MODELS . 2-42-2.5 REGISTER-TRANSFER MODELS . 2-42-2.6 GATE-LEVEL MODELS . 2-42-2.7 USES OF ABSTRACTION AND HIERARCHICAL DECOMPOSITION IN THE DESIGN PROCESS 2-52-3 BEHAVIORAL DESCRIPTIONS OF HARDWARE DESIGNS . 2-52-3.1 T

20、HE PURPOSE OF BEHAVIORAL DESCRIPTIONS 2-52-3.2 THE USE OF HIERARCHY IN BEHAVIORAL DESCRIPTIONS . 2-62-3.3 EXAMPLE OF A BEHAVIORAL DESCRIPTION 2-72-4 STRUCTURAL DESCRIPTIONS OF HARDWARE DESIGNS . 2-122-4.1 THE PURPOSE OF STRUCTURAL DESCRIPTIONS 2-122-4.2 THE USE OF HIERARCHY IN STRUCTURAL DESCRIPTION

21、S . 2-132-4.2.1 Hierarchical Decomposition Based on Physical Elements . 2-132-4.2.2 Leaf Modules in a Hierarchical Structural Description 2-142-4.3 EXAMPLES OF STRUCTURAL DESCRIPTIONS . 2-142-4.3.1 Algorithmic-Level Structural Description 2-142-4.3.2 Register-Transfer-Level Structural Description .

22、2-202-5 MIXED ABSTRACTION MODELS . 2-222-5.1 THE PURPOSE OF MIXED LEVEL OF ABSTRACTION MODELS 2-222-5.2 DESIGNING MODULES FOR MIXED ABSTRACTION MODELS 2-222-5.3 AN EXAMPLE OF A MIXED LEVEL OF ABSTRACTION MODEL . 2-23REFERENCES . 2-23BIBLIOGRAPHY 2-24Provided by IHSNot for ResaleNo reproduction or ne

23、tworking permitted without license from IHS-,-,-MIL-HDBK-62ivCHAPTER 3VHDL CONCEPTS3-1 INTRODUCTION 3-13-2 BASIC VHDL CONCEPTS . 3-13-2.1 VHDL DESIGN ENTITIES 3-13-2.1.1 Entity Interfaces 3-23-2.1.2 Architecture Bodies 3-33-2.2 THE VHDL CONCEPT OF TIME . 3-43-2.3 SIGNALS 3-43-2.3.1 Signal Assignment

24、 Statements . 3-43-2.3.2 Resolution Functions 3-53-3 VHDL SUPPORT FOR BEHAVIORAL DESIGN . 3-63-3.1 PROCESSES . 3-63-3.2 WAIT STATEMENTS 3-73-3.3 A BEHAVIORAL DESIGN EXAMPLE 3-73-4 VHDL SUPPORT FOR STRUCTURAL DESIGN .3-83-4.1 STRUCTURAL ARCHITECTURE BODIES 3-83-4.2 COMPONENTS 3-83-4.2.1 Component Dec

25、larations 3-83-4.2.2 Component Instantiations and Interconnections . 3-93-4.3 A STRUCTURAL DESIGN EXAMPLE . 3-93-5 VHDL SUPPORT FOR DATA ABSTRACTION . 3-103-5.1 USER-DEFINED TYPES . 3-113-5.2 TYPE CONVERSION FUNCTIONS . 3-113-5.3 OVERLOADED OPERATORS . 3-123-6 VHDL SUPPORT FOR ANNOTATING MODELS . 3-

26、123-6.1 ATTRIBUTES . 3-123-6.2 GENERIC CONSTANTS . 3-133-6.3 PHYSICAL TYPES 3-133-7 ERROR HANDLING WITH VHDL 3-143-7.1 ASSERTION STATEMENTS 3-143-7.2 HANDLING SIGNAL ERROR STATES 3-153-8 VHDL SUPPORT FOR SHARING AND REUSE 3-153-8.1 VHDL DESIGN LIBRARIES . 3-163-8.1.1 Declaring and Using Libraries 3-

27、163-8.1.2 Constructing Libraries 3-193-8.2 VHDL PACKAGES 3-203-8.2.1 Constructing VHDL Packages 3-203-8.2.2 Declaring and Using Packages . 3-203-8.3 CONFIGURATION SPECIFICATIONS AND DECLARATIONS 3-203-8.3.1 Constructing Configuration Specifications and Declarations 3-213-8.3.2 Using Configuration Sp

28、ecifications and Declarations 3-22REFERENCES 3-24BIBLIOGRAPHY . 3-24CHAPTER 4DoD REQUIREMENTS FOR THE USE OF VHDL4-1 INTRODUCTION 4-14-2 MIL-HDBK-454 GUIDELINES FOR THE USE OF VHDL 4-14-2.1 DOCUMENTATION OF ASICs DEVELOPED FOR THE GOVERNMENT WITH VHDL . 4-14-2.2 DOCUMENTATION OF QUALIFIED DIGITAL IN

29、TEGRATED CIRCUITS WITH VHDL . 4-24-2.3 THE LIBRARY OF VHDL DESCRIPTIONS OF STANDARD DIGITAL PARTS 4-24-2.4 TEST BENCH REQUIREMENTS FOR VHDL DESCRIPTIONS 4-24-3 OVERVIEW OF THE VHDL DATA ITEM DESCRIPTION 4-24-3.1 ENTITY INTERFACE REQUIREMENTS 4-3Provided by IHSNot for ResaleNo reproduction or network

30、ing permitted without license from IHS-,-,-vMIL-HDBK-624-3.1.1 Entity Names 4-34-3.1.2 Input and Output Definitions 4-34-3.2 BEHAVIORAL DESCRIPTIONS 4-44-3.2.1 Functional Decomposition 4-44-3.2.2 Timing Descriptions . 4-54-3.3 STRUCTURAL DESCRIPTIONS 4-54-3.3.1 Acceptable Primitive Elements 4-54-3.3

31、.2 Testability Requirements 4-54-3.4 TEST BENCH REQUIREMENTS . 4-64-3.4.1 Test Bench Functions . 4-64-3.4.2 Test Bench Relationships to Design Modules 4-74-3.5 ERROR MESSAGES 4-74-3.6 DOCUMENTATION FORMAT 4-74-3.7 REQUIRED ANNOTATIONS OF VHDL MODULES . 4-84-3.8 AN EXAMPLE OF A TAILORED DID 4-8REFERE

32、NCES 4-8BIBLIOGRAPHY . 4-9CHAPTER 5 CONSTRUCTION OF BEHAVIORAL VHDL MODELS5-1 INTRODUCTION 5-15-2 CREATION OF VHDL BEHAVIORAL MODELS 5-15-2.1 CONSTRUCTING PERFORMANCE MODELS 5-15-2.1.2 Modeling Timing in Performance- and Algorithmic-Level Behavioral Models 5-25-2.1.3 Example of a Statistics Package

33、and Its Use 5-25-2.2 CONSTRUCTING ALGORITHMIC MODELS 5-65-2.2.1 Modeling Algorithms With VHDL Processes 5-75-2.2.2 An Example of an Algorithmic Model .5-75-2.3 CONSTRUCTING INSTRUCTION-SET-ARCHITECTURE-LEVEL MODELS . 5-115-2.3.1 Modeling Processors . 5-115-2.3.2 Modeling Memory 5-175-2.3.3 Modeling

34、Busses and Bus Controllers 5-185-2.4 CONSTRUCTING REGISTER-TRANSFER-LEVEL MODELS . 5-195-2.4.1 Synthesis of Designs From RTL Models . 5-195-2.4.2 An Example of a VHDL Register-Transfer-Level Model 5-205-3 VHDL DID SIMULATION REQUIREMENTS FOR BEHAVIORAL MODELS 5-215-3.1 CORRECT FUNCTIONAL RESPONSE TO

35、 STIMULI . 5-215-3.2 SIMULATION TIMING . 5-215-3.3 ERROR HANDLING 5-215-4 TIMING IN BEHAVIORAL MODELS 5-225-4.1 TIMING SHELLS . 5-225-4.2 CLOCK RATES 5-245-4.3 CRITICAL PATH DELAY TIMES 5-245-4.4 BEST-CASE, WORST-CASE, AND NOMINAL DELAYS . 5-245-4.5 PARAMETERIZED DELAY MODELS 5-245-4.6 TIMING DEFINI

36、TION PACKAGE . 5-265-4.7 TIMING THROUGH FILE INPUT 5-315-4.8 MODELING ASYNCHRONOUS TIMING 5-325-4.9 MODELING SYNCHRONOUS TIMING . 5-335-5 ANNOTATION OF BEHAVIORAL MODELS 5-365-5.1 DESCRIPTION OF FUNCTION 5-365-5.2 DESCRIPTION OF RESTRICTIONS 5-365-5.3 MODELING APPROACH . 5-365-5.4 REVISION HISTORY 5

37、-375-5.5 BACK ANNOTATION OF TIMING INFORMATION 5-37Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-HDBK-62vi5-6 USE OF STRUCTURAL HIERARCHY IN BEHAVIORAL MODELS 5-37REFERENCES . 5-38BIBLIOGRAPHY 5-38CHAPTER 6 CONSTRUCTION OF STRUCTURAL VHDL MODEL

38、S6-1 INTRODUCTION 6-16-2 CREATION OF STRUCTURAL VHDL MODELS .6-16-2.1 TRANSLATION OF SCHEMATIC CAPTURE MODELS 6-16-2.2 SYNTHESIS OF STRUCTURAL MODELS FROM REGISTER-TRANSFER-LEVEL MODELS .6-26-2.3 SYNTHESIS OF STRUCTURAL MODELS FROM FINITE STATE MACHINES .6-26-2.4 ENHANCEMENT OF GATE-LEVEL MODELS WIT

39、H GENERATED STRUCTURE .6-26-3 VHDL DID ORGANIZATIONAL REQUIREMENTS FOR STRUCTURAL MODELS .6-36-3.1 HIERARCHICAL ORGANIZATION OF STRUCTURAL MODELS .6-36-3.2 ALLOWABLE LEAF-LEVEL MODULES .6-46-3.2.1 Government-Approved Models 6-46-3.2.2 Modules With Stimulus-Response Behavior 6-46-3.2.3 Modules Withou

40、t Detailed Designs 6-46-3.3 VHDL DID ANNOTATION REQUIREMENTS FOR STRUCTURAL MODELS .6-56-3.3.1 Physical View Requirements 6-66-3.3.2 Electrical View Requirements 6-66-3.3.3 Timing View Requirements 6-76-4 VHDL DID SIMULATION REQUIREMENTS FOR STRUCTURAL MODELS 6-96-4.1 SUPPORT FOR LOGIC-LEVEL FAULT M

41、ODELING .6-96-4.2 SUPPORT FOR TEST VECTOR GENERATION 6-106-5 TIMING SPECIFICATIONS FOR STRUCTURAL MODELS 6-106-6 BACK ANNOTATION OF STRUCTURAL MODELS . 6-116-6.1 BACK ANNOTATION OF TIMING INFORMATION 6-116-6.2 BACK ANNOTATION OF LAYOUT INFORMATION 6-126-6.3 BACK ANNOTATION OF TESTABILITY INFORMATION

42、 . 6-12REFERENCES . 6-12BIBLIOGRAPHY 6-13CHAPTER 7 PREPARATION OF VHDL MODELS FOR SIMULATION7-1 INTRODUCTION 7-17-2 INTEROPERABILITY OF MODELS . 7-17-2.1 USE OF STANDARD SIGNAL DATA TYPES 7-27-2.2 TYPE CONVERSION FOR DIFFERENT SIGNAL DATA TYPES 7-27-2.3 INTEROPERABILITY OF TIMING MODELS 7-37-2.4 POR

43、TABILITY REQUIREMENTS FOR INTEROPERABLE VHDL MODELS . 7-37-3 TEST BENCH DEVELOPMENT 7-37-3.1 WAVES . 7-47-3.1.1 Standard WAVES Packages . 7-77-3.1.2 Local WAVES Packages 7-87-3.1.3 WAVES Test Suites . 7-87-3.2 DOCUMENTATION OF TEST BENCHES 7-107-4 TEST VECTOR DEVELOPMENT . 7-107-4.1 BEHAVIOR TESTS 7

44、-107-4.2 PROPAGATION DELAY TESTS . 7-117-4.3 ERROR CONDITION TESTS 7-117-4.3.1 Invalid Operating Condition Tests . 7-127-4.3.2 Invalid Input State Tests . 7-127-4.3.3 Timing Constraint Violation Tests . 7-12Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS

45、-,-,-viiMIL-HDBK-627-4.4 INTEROPERABILITY TESTS 7-137-4.5 ORGANIZATION AND DOCUMENTATION OF TEST VECTORS . 7-137-5 USE OF CONFIGURATION DECLARATIONS TO INSTANTIATE THE TEST BENCH FOR A MODEL . 7-147-5.1 SELECTION OF ALTERNATIVE DESIGN LIBRARIES . 7-147-5.2 SELECTION OF ALTERNATIVE ARCHITECTURES . 7-

46、157-5.3 BINDING OF GENERICS 7-157-5.4 PORT MAPPING 7-157-6 DEFINITION OF SIMULATOR OPTIONS 7-157-6.1 CONTROL OVER ENVIRONMENTAL PARAMETERS . 7-167-6.2 SELECTION OF DELAY TYPES . 7-167-6.3 CONTROL OVER EXECUTION OF ASSERTIONS . 7-167-6.4 CONTROL OVER PROPAGATION OF UNKNOWN SIGNAL STATES . 7-16REFEREN

47、CES . 7-17BIBLIOGRAPHY 7-17CHAPTER 8MODELING TESTABILITY WITH VHDL MODELS 8-1 INTRODUCTION 8-18-2 PURPOSE AND SCOPE OF DESIGN FOR TESTABILITY . 8-18-3 TESTABILITY DESIGN ISSUES . 8-18-3.1 TEST STRATEGIES AND TECHNIQUES FOR MAINTENANCE AND FAULT TOLERANCE . 8-28-3.2 TESTABILITY MEASURES . 8-38-3.3 TE

48、ST STRUCTURE BOUNDARIES 8-48-3.4 TEST COMPONENTS AND INTERFACES 8-68-4 MODELING TESTABILITY USING VHDL BEHAVIORAL MODELS . 8-68-4.1 EVALUATING TEST STRATEGIES . 8-68-4.2 MODELING TEST INTERFACES IN VHDL . 8-78-4.3 MODELING TEST CONTROLLER FUNCTIONS 8-78-4.4 EVALUATION OF TEST COMMUNICATION AND STORA

49、GE REQUIREMENTS FOR BIT . 8-78-5 MODELING TESTABILITY USING VHDL STRUCTURAL MODELS . 8-78-5.1 DESCRIPTION OF TEST CIRCUITRY GENERATED FROM STRUCTURAL INFORMATION 8-78-5.2 SUPPORT FOR FAULT DICTIONARY GENERATION 8-88-5.3 SUPPORT FOR AUTOMATIC TEST GENERATION 8-88-5.4 SUPPORT FOR COVERAGE ANALYSIS . 8-88-5.5 SUPPORT FOR TEST TIME COMPUTATION . 8-88-6 ANNOTATION OF VHDL MODELS WITH TESTABILITY INFORMATION 8-88-6.1 ANNOTATION OF STRUCTURAL MODELS T