DLA DSCC-VID-V62 03664 REV B-2012 MICROCIRCUIT DIGITAL LOW VOLTAGE CMOS 8-CHANNEL ANALOG MULTIPLEXER DEMULTIPLEXER MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add case outlines Y and Z. - CFS 04-03-08 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 12-06-04 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Pre
2、pared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Original date of drawing CHECKED BY Charles
3、F. Saffle TITLE MICROCIRCUIT, DIGITAL, LOW VOLTAGE CMOS, 8-CHANNEL ANALOG MULTIPLEXER/ DEMULTIPLEXER, MONOLITHIC SILICON YY-MM-DD 03-10-07 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/03664 REV B PAGE 1 OF 15 AMSC N/A 5962-V066-12 .Provided by IHSNot for ResaleNo reproduction
4、or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03664 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 8-channel analog multiplexer/demultiplexer microcir
5、cuit, with an operating temperature range of -40C to +105C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/
6、03664 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 74LV4051A-EP 8-channel analog multiplexer/demultiplexer 1.2.2 Case outline. The case outline are as specified herein. Outline letter Nu
7、mber of pins JEDEC PUB 95 Package style X 16 JEDEC MO-153 Plastic small-outline Y 16 JEDEC MS-012 Plastic small-outline Z 16 JEDEC MS-013 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designat
8、or Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03664 REV B P
9、AGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to +7.0 V Input voltage range (VI) . -0.5 V to +7.0 V 2/ Switch I/O voltage range (VIO) . -0.5 V to VCC+ 0.5 V 2/ 3/ Input clamp current (IIK) (VIVCC) . 50 mA Switch through current (IT) (VIO= 0 to VCC) . 25 mA Continuous cur
10、rent through VCCor GND . 50 mA Package thermal impedance (JA): 4/ Case outline X . 108C/W Case outline Y . 73C/W Case outline Z . 57C/W Storage temperature range (TSTG) . -65C to +150C 1.4 Recommended operating conditions. 5/ Supply voltage range (VCC) . 2.0 V to 5.5 V 6/ Minimum high level input vo
11、ltage (VIH), control inputs: VCC= 2.0 V 1.5 V VCC= 2.3 V to 2.7 V . VCCx 0.7 VCC= 3.0 V to 3.6 V . VCCx 0.7 VCC= 4.5 V to 5.5 V . VCCx 0.7 Maximum low level input voltage (VIL), control inputs: VCC= 2.0 V 0.5 V VCC= 2.3 V to 2.7 V . VCCx 0.3 VCC= 3.0 V to 3.6 V . VCCx 0.3 VCC= 4.5 V to 5.5 V . VCCx
12、0.3 Control input voltage range (VI) . 0.0 V to 5.5 V Input/output voltage range (VIO) 0.0 V to VCCMaximum input transition rise or fall rate (t/v): VCC= 2.3 V to 2.7 V . 200 ns/V VCC= 3.0 V to 3.6 V . 100 ns/V VCC= 4.5 V to 5.5 V . 20 ns/V Operating free-air temperature range (TA) -40C to +105C 2.
13、APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or f
14、rom JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any othe
15、r conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
16、 3/ This value is limited to 5.5 V maximum. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. 5/ All unused inputs of the device must be held at VCCor GND to ensure proper device operation. 6/ With supply voltages at or near 2 V, the analog switch on-state resistance becom
17、es very nonlinear. It is recommended that only digital signals be transmitted at these low supply voltages. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03664 R
18、EV B PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shal
19、l be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and phy
20、sical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown in 1.2.2 and figure 1. 3.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be
21、as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuits. The timing waveforms and test circuits shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without licen
22、se from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/03664 REV B PAGE 5 TABLE I. Electrical performance characteristics. Test Symbol Conditions VCCTemperature, TALimits Unit Min Max On-state switch resistance ronIT= 2 mA VI= VCCor GND VINH= VILSee fi
23、gure 5 2.3 V 25C 180 -55C to 125C 225 3.0 V 25C 150 -55C to 125C 190 4.5 V 25C 75 -55C to 125C 100 Peak on-state resistance ron(p)IT= 2 mA VI= VCCor GND VINH= VIL2.3 V 25C 500 -55C to 125C 600 3.0 V 25C 180 -55C to 125C 225 4.5 V 25C 100 -55C to 125C 125 Difference in on-state resistance between swi
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