SMPTE EG 33-2004 Jitter Characteristics and Measurements《抖动特性和测量》.pdf

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1、Page 1 of 13 pages Introduction Transferring digital signals from one location to another involves converting the signals into an analog physical representation at the sending end and then interpreting that representation to extract the data at the receiving end. This is necessary because any signal

2、s that are physically represented inherently have analog properties. These properties include the levels and timing of the data intervals and the transitions between them, the spectral distribution that results, and any signal distortions that occur in the transmission system. This is true whether t

3、he signals are modulated onto an RF carrier or transmitted directly as data using an appropriate form of encoding. Analog effects that can alter digital signals are attenuation, spectral roll-Offs and anomalies, overshoots, undershoots, time dispersion, and jitter. The first several are frequency- a

4、nd amplitude-related effects while jitter is the sole timing-related disturbance. 1 Scope This guideline examines the types of jitter in directly transmitted data signals, the methods for measuring each one, and some of the impacts they can have on system operation. Additionally, some of the system

5、design approaches that can minimize or mitigate the impact of jitter are presented. 2 Jitter definition In this guideline, the 270 Mbits/s (Mb/s) serial digital interface (SDI) signals of SMPTE 259M will be used as an example, but the same concepts apply to serially transmitting everything from 3.1

6、Mb/s AES3 audio data streams through 1.5 Gb/s HDTV versions of the SDI. Only the numerical values used for equipment specifications and measurements change when covering this large range of digital signals. To send digital data streams from one place to another over a single wire or fiber, data is e

7、ncoded using one of several self-clocking methods. These include such schemes as NRZ, NRZI, bi-phase mark, and others which typically trade-off the resulting data signal bandwidth and spectral shaping for ease of clock extraction, error detection ability, or other performance features. The important

8、 thing about all of these designs is that they allow the clock to be extracted from the data stream so it can be used to recover the data. Clocking information is usually extracted using phase lock loop circuits. The transition locations in a data stream are instantaneously compared with transitions

9、 of a synthesized clocking signal coming from a local oscillator (typically an RC- or LC-type voltage controlled oscillator) at the receiver. The local clocks frequency is then adjusted up or down until the extracted clocks edges agree with the incoming data edges. This process is straightorward as

10、long as the data transitions occur at the expected intervals; that is, integer multiples of the serial clock period. In real systems, however, the data transitions will deviate somewhat from their ideal position; that is, the pulse positions vary with respect to a high stability frequency-locked clo

11、ck. This unwanted pulse position variation is jitter. Approved November 30,2004 Copyight O 2004 by THE SOCIETY OF MOTION PICTURE AND TELEVISION ENGINEERS (914) 761-1100 595 W. Harisdale Ave., White Plains, NY 10607 EG 33-2004 Jitter is defined as the variation of a digital signals significant instan

12、ts (such as transition points) from their ideal positions in time. Jitter can cause the recovered clock and the data to become momentarily misaligned in time. Data may be misinterpreted (latched at the wrong time) when this misalignment becomes great enough. Jitter is measured in terms of the unit i

13、nterval (U), which represents the period of one clock cycle and, for NRZ or NRZI encoded data, corresponds to the nominal minimum time between transitions of the serial data. This can be seen in figure la, where the data of an NRZI signal and the related clock ticks are shown. Figure 1 b shows the e

14、ffect of jitter on the midpoint crossings of the data transitions, as would be seen on an eye-pattern presentation (repetitive display of transition points overlaid upon one another). Increasing jitter closes the eye in the time dimension and makes decisions between data states correspondingly more

15、difficult, just as signal voltage noise does in the amplitude dimension. Jitter, then, can be thought of as the phase variation (or modulation) of the serial data stream. This phase modulation has a spectrum that corresponds to the frequency with which the datas clock is modulated. Thus, it is possi

16、ble to plot an amplitude versus frequency characteristic of the jitter. For example, in figure 2, a single spike at 6144 Hz indicates the presence of sinusoidal phase variation (jitter) at a rate of 6144 Hz. The amplitude of the spike would indicate how much of the data eye was closed. 3 Classes of

17、jitter Absolute jitter is the aggregate of all jitter frequency components found in a signal, from very low to very high frequency. Measuring exact absolute jitter is practically impossible because it is difficult to generate an absolute reference defining where data edges should be. The practical s

18、tudy of jitter divides it into three classes, based on the frequency content of the jitter modulation. The very lowest frequency variations in the positions of a signals transitions are termed wander. Wander typically has no effect on the capability of the clock extraction and decoding electronics t

19、o accurately recover the digital data stream because this low-frequency variation can be followed by the PLL (unless the wander causes the data rate to go outside the range of the controlled reference oscillator). Wander may, however, cause problems in later downstream processing. Wander is generall

20、y defined as jitter with frequency components below a particular frequency. In SDI applications, this assigned cutoff is 10 Hz. Measuring wander and absolute jitter implies that the clocking reference used to identify edge jitter be extremely stable with no jitter component of its own. Typical PLL-e

21、xtracted clocks are unsuitable for this measurement. The source of such an accurate reference signal might be a high-Q crystal oscillator; however, access to this type of signal is not common in SDI applications. This limitation typically causes wander to be excluded in jitter measurements. Jitter t

22、hat occurs above the highest frequency defined as wander is termed timing jitter. Jitter that is measured relative to a recovered clock with a loop bandwidth defined by f3 (figure 3) is called alignment jitter. The difference between timing jitter and alignment jitter is the low-frequency jitter. Th

23、e timing jitter measurement is used to provide an idea of how the overall system is performing. It can be measured by setting the loop filter bandwidth of the clock recovery system to fl. The result will include all frequencies of jitter above the loop filter cutoff to the upper limit of the measure

24、ment. This broadband measurement will not specifically identify jitter that could cause data recovery errors. Alignment jitter can provide information on jitter that directly affects the receivers ability to properly recover data. This type of error occurs because the PLL is not able to track the ti

25、ming changes of the incoming signal. If the timing errors become large enough, the decoder will “slip“ a bit, which will cause an error in the decoded data. This produces a word framing error, which will not be corrected until the next timing reference signal. Low-frequency jitter generally does not

26、 cause problems in the serial link. Large amounts of low-frequency jitter can be tolerated by the serial link, as the PLL follows these timing changes and maintains proper data recovery. However, one must be aware of this band of jitter, as it will be present in the recovered parallel clock. This pa

27、rameter is important to monitor if the recovered clock is to be used as a reference signal in the parallel domain. Page 2 of 13 pages EG 33-2004 Data a) Relationship of Data 2) This scaled jitter is added to the equipments intrinsic jitter to get output jitter; 3) This output jitter becomes the inpu

28、t jitter for the next stage, and the process repeated; 4) At no point can the output jitter exceed the input jitter tolerance of the next stage. Example: fl=10 Hz fl=10 Hz fl=10 Hz f3=1 kHz f3=1 kHz f2=20 kHz f4=27 MHz fl=10 Hz f4=27 MHz f3=1 O0 kHz A10.5 u1 fc= 1 MHz Alz0.2 u1 f4=5 MHz A1=2.5 UI A2

29、=0.5UI I lunit jitter tolerance I A20.1 u1 I I p= 0.5 dB1 I A20.15 u1 I Output jitter Unit B jitter Unit B intrinsic from Unit A transfer jitter Step 1 : Multiplv output iitter from unit A bv unit Bs iitter transfer function Unit Bs jitter transfer function shows 0.5 dB peaking over 10 Hz to 1 MHz,

30、rolling off beyond 1 MHz. 0.5 dB corresponds to a gain of 1.06. fl to fc (IO Hz to 1 MHz): (Al)log-(P/20) = (0.5 Ui) (1.06) = 0.53 U1 f3 to fc (1 kHz to 1 MHz): (A2)log-I (P/20) = (0.1 Ui) (1.06)= 0.1 1 UI Note that the jitter calculation was limited to 1 MHz (fc), even though the input jitter (outp

31、ut jitter from unit A) was specified to 27 MHz (f4). This is because unit Bs jitter transfer function low pass filters the input jitter to 1 MHz. Even if higher frequency terms are present, they are not propagated by unit B and hence do not figure into the accumulation calculation. Page 10 of 13 pag

32、es EG 33-2004 Step 2: Add unit B intrinsic iitter to iitter transferred bv unit B to cret unit B output iitter Above fl (IO Hz): Output jitter = 0.53 UI + 0.2 UI = 0.73 UI Above f3 (1 kHz): Output jitter = 0.1 1 UI + 0.15 UI = 0.26 UI Above fc (1 MHz): Output jitter = 0.15 UI The third entry results

33、 because there is no jitter transfer above fc (1 MHz). Thus, the only output jitter above this frequency is unit Bs intrinsic jitter. Although it is unknown if the 0.15 UI occurs between 1 kHz and 1 MHz, or above 1 MHz, the practice is to assume a constant magnitude over the entire f3 to f4 range. S

34、tep 3: Compare unit B output iitter with unit C input iitter tolerance Unit C jitter tolerance requires that jitter above f3 (100 kHz) must be less than 0.5 UI, and jitter between fl (IO Hz) and f2 (20 kHz) must be less than 2.5 UI. Unit B output jitter is 0.15 UI above fc (1 MHz), 0.26 UI above f3

35、(1 kHz), and 0.73 UI above fl (IO Hz). A pessimistic but convenient assumption is that all 0.73 UI occurs between fl and f3 (IO Hz and 1 kHz). Note that unit Bs output jitter is less than unit Cs input jitter tolerance (see figure 12). Thus, this cascade of equipment would work. I 2.5UI unit B Unit

36、C jitter tolerance y I )utput jilter O. 15U I 10 Ik 20k 100k 1M frequency (Hz) Figure 12 - Unit B output jitter compared with unit C jitter tolerance The simple method described above allows paper calculations of a proposed cascade of equipment. This requires obtaining jitter tolerance, jitter trans

37、fer, and intrinsic jitter specifications from the equipment manufacturer. If unavailable, these parameters can be measured. Jitter failures result when output jitter exceeds the following equipments input jitter tolerance. Common causes of this in a system are: 1) Excessive intrinsic jitter, normall

38、y the result of poor equipment design or equipment failure; Page 11 of 13 pages EG 33-2004 2) After a cascade of equipment having jitter transfer up to fc, adding a device whose jitter tolerance breakpoint f3 is much lower than frequency fc. Jitter will accumulate arithmetically below fc, and will e

39、ventually exceed the high-frequency jitter tolerance A2. There is essentially no jitter accumulation above fc; 3) Peaking in the jitter transfer function, usually near fc (see figure 13). A cascade of equipment with this characteristic can show pronounced jitter growth. Items 2 and 3 are good exampl

40、es of why published specifications on jitter transfer and jitter tolerance are important. Item 2 can be avoided by suitable equipment choice, by suitably ordering a cascade of equipment, or by installing a jitter remover prior to the device with the low f3 jitter tolerance breakpoint. Item 3 can be

41、avoided with suitable equipment choice (small jitter peaking), or designed around jitter removers, or by limiting the length of the cascade. All of these solutions require knowing the jitter transfer and tolerance of components in the system. P Jitter Transfer Gain .m PLL Loop Overshoot Template Mna

42、siirnd J ittnr Specification fl fc Jitter Frequency Figure 13 -Jitter transfer function showing jitter peaking 7 Mitigating jitter It may be necessary to eliminate jitter at various points in a system. This could be for reasons of jitter accumulation sufficient to exceed the input jitter tolerance o

43、f a succeeding device, as just discussed, or it could be to permit a high-quality conversion to analog form. Jitter causes non-linearity in digital-to-analog (D/A) converters. High quality D/A conversion, therefore, requires removal of any jitter accompanying a signal if the conversion clock is deri

44、ved from the signal. A jitter remover works by converting serial digital signals back to parallel form, passing them through a first-in- first-out (FIFO) register, and then re-serializing them using a highly stable clock. Usually this highly stable Page 12 of 13 pages EG 33-2004 clock is referenced

45、to a synchronization signal like black burst. As shown in figure 14, the input to the jitter remover is structured very much like the input to any equipment with an SDI input. This is followed by a relatively small FIFO with sufficient length to accommodate the longest time variations caused by the

46、highest jitter amplitudes expected to be encountered. Finally, the high quality clock source drives either a serializer or a D/A converter to provide a virtually jitter-free output. Devices of this sort can be applied in a system as often as necessary to control jitter accumulation or to ensure line

47、ar analog outputs. Care must be taken in implementing jitter removers to account for the additional delay they cause and to ensure that the delay is predictable. Serial out Deserialiser recovery Serial clock I with jitter 11 Clock Parallel clock + - . recovery with jitter Low jitter clock High Q +El

48、 VI II I I. Analog out - Figure 14 - Block diagram of a “jitter remover“ Annex A (informative) Bibliography AES3-2003, Digital Audio Engineering - Serial Transmission Format for Two-Channel Linearly Represented Digital Audio Data SMPTE 259M, Television - SDTV Digital Signal Data - Serial Digital Interface Page 13 of 13 pages