JEDEC JESD8-9B-2002 Stub Series Terminated Logic for 2 5 Volts (SSTL 2)《2 5伏的短系列终止逻辑(SSTL 2) 勘误 2002年10月18日》.pdf

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1、October 18,2002 ERRATA TO JEDEC STANDARD JESDS-9B, - ADDENDUM NO. 9B to JESDS - STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL-2) REASON FOR ERRATA: Days after publication of this standard in May 2002, it was brought to the attention of the sponsor that there were errors in Table 4. ARer firher in

2、vestigation by the sponsor it was noted that during the transfer of numbers from the worksheet to FrameMaker a couple of typos had been introduced. These typos had gone unnoticed through the complete ballot process. The sponsor presented the corrected numbers to the committee at its September 2002 m

3、eeting and Table 4 as corrected was approved. HARD COPY All recipients of this errata are asked to replace page 7 with the corrected page included in this errata. ELECTRONIC: If you have downloaded the file prior to date of errata please reprint page 7. The sheet has been corrected in the downloadab

4、le file on the JEDEC website as of October 18,2002. The standard in question can be downloaded at no charge from the JEDEC web site at www.jedec.org. # # # JEDEC is the leading developer of standards for the solid-state industry, they have published over 800 documents to date. Almost 1800 representa

5、tives, appointed by some 250 JEDEC member companies work together in 50 JEDEC committees to meet the needs of every segment of the industry, manufacturers and consumers alike. The Standards, Publications, and Outlines that they generate are accepted throughout the world. All JEDEC standards are avai

6、lable online, at no charge. To access JEDEC documents or obtain further information, visit the JEDEC web page, at wvw.,jcdcc.org. JEDEC is a sector ofthe Electronic Industries Alliance (EIA). 2500 Wilson Boulevard Arlington, Virginia 222013834 (703) 9077559 FAX (703) 9077583 JEDEC Standard No. 8-9B

7、corrected Page 7 3 SSTL-2 Output buffers (contd) 3.1 Overview (contd) Table 4 - Spread sheet showing how the limits of SSTL-2 circuit voltages Output High Drive 365 365 365 365 365 365 405 Output Low Drive mV -365 -365 -365 -365 -365 -365 -405 NOTE 1 exactly and then rounded. Bold numbers resemble t

8、he (exact) system assumptions; the other numbers are calculated NOTE 2 Table 4 does not take into account 2% VE, (Ac) noise ( +/- 25 mV nominal) which will further reduce the effective A Vmwm) at the receiver. JEDEC STANDARD Stub Series Terminated Logic for 2.5 V (S STL-2) JESDS-9B (Revision of JESD

9、S-9A) MAY 2002 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. JEDEC standards and publications are desi

10、gned to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC me

11、mbers, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent ow

12、ner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint.

13、Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an EIA standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and su

14、ggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC, address below, or call (703)907-7559 or www.jedec.org. Published by OJEDEC Solid State Technology Association 2002 2500 Wilson Boulevard Arlington, VA 22201-3834 This documentmay be downloaded free

15、of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. Price: Please refer to the current Catalog of JEDEC Engineering Standards and Publications or call Global Engineering Documents, USA and

16、 Canada (1-800-854-7179), International (303-397-7956) Printed in the U.S.A. All rights reserved JEDEC Standard No. 8-9B STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL-2) A 2.5 V Supply Voltage Based Interface Standard for Digital Integrated Circuits CONTENTS Foreword 1 Scope 1.1 Standard Structur

17、e 1.2 Rationale and assumptions 2 Supply voltage 2.1 Supply voltage levels 2.2 Input parametric 2.3 AC test conditions 3 SSTL-2 output buffers 3.1 Overview 3.2 SSTL-2 Class I output buffers 3.2.1 Push-pull output buffer for symmetrically single parallel terminated loads with series resistor (VTT = 0

18、.5 x VDDQ). 3.2.2 SSTL-2 Class I output ac test conditions 3.3 SSTL-2 Class II output buffers 3.3.1 Push-pull output buffer for symmetrically double parallel terminated loads with series resistor (VTT = 0.5 x VDDQ). 3.3.2 SSTL-2 Class II output ac test conditions 4 Other applications 4.1 Push-pull o

19、utput buffer for unterminated loads 4.2 Push-pull output buffer for symmetrically single parallel terminated loads (VTT = 0.5 x VDDQ). Page iv 1 1 1 2 3 3 4 5 5 8 8 9 10 10 11 11 11 12 -1- JEDEC Standard No. 8-9B STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL-2) A 2.5 V Supply Voltage Based Interf

20、ace Standard for Digital Integrated Circuits CONTENTS 4.3 Push-pull output buffer for externally source series terminated loads 4.4 Push-pull output buffer for symmetrically double parallel terminated loads (VTT = 0.5 x VDDQ) 5 Differential signals 5.1 Overview 5.2 Differential input parameters 5.3

21、AC test conditions 5.4 Example of SSTL-2 Class I differential signal 5.4.1 Example of SSTL-2 Class I differential clock signals (For reference only) Figures 1 SSTL-2 Input voltage levels 2 AC Input test signal wave form 3 Typical output buffer (driver) environment 4 Example of SSTL-2, Class I, symme

22、trically single parallel terminated output load, and series resistor 5 Example of SSTL-2, Class II, symmetrically double parallel terminated output load with series resistor 6 Example of SSTL-2 unterminated output load 7 Example of SSTL-2, Class I or Class II, buffer with symmetrically single parall

23、el terminated output loads 8 Example of SSTL-2, Class I or Class II, Externally Source Series terminated output load Page 13 13 14 14 14 15 17 18 10 12 12 13 -11- JEDEC Standard No. 8-9B STUB SERIES TERMI IATED ,OGIC FOR 2.5 VOLTS (SSTL-2) A 2.5V Supply Voltage Based Interface Standard for Digital I

24、ntegrated Circuits CONTENTS 9 Example of SSTL-2, Class I, buffer with symmetrically double parallel terminated output load 1 O SSTL-2 differential input levels 11 Differential ac input test signal wave form 12 Example of SSTL-2 class I, differential signal using single load, and series resistor 13a

25、Example of SSTL-2 class I, differential signal using direct termination resister, and series resistor (Reference only) 13b Input clock signal offset voltage (Reference only) Tables 1 Supply voltage levels 2a Input dc logic levels 2b Input ac logic levels 3 AC input test conditions 4 Examples of how

26、the limits of SSTL-2 circuit voltages depending on V,DQ 5a Output dc current drives 5b AC test conditions 6 Output dc current drive 7 AC test conditions 8a Differential input dc logic levels 8b Differential input ac logic levels 9 Differential input ac test conditions 1 O Viso specifications (Refere

27、nce only) Page 14 15 17 17 18 19 3 3 4 4 7 8 9 10 11 14 15 16 18 . -111- JEDEC Standard No. 8-9B STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL-2) A 2.5 V Supply Voltage Based Interface Standard for Digital Integrated Circuits Foreword The folowing changes are included in this revision: Reduction

28、of VIH/VIL (AC) from 350 mV to 3 1 O mV and of VIL/VIH (DC) from 180 mV to 150 mV (single ended applications); increase of driver current from 15.4 mA (7.6 mA) to 16.2 mA (8.1 mA); reduction of VIH/VIL (AC) from 700 mV to 620 mV and of VIH/VIL (DC) from 360 mV to 300 mV (differential applications.);

29、 recalcu- lation of Table 4. -iv- JEDEC Standard No. 8-9B Page 1 STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL-2) A 2.5 V Supply Voltage Based Interface Standard for Digital Integrated Circuits From JEDEC Board Ballots JCB-97-80 and JCB-98-80 (section 5), and JCB-01-87, formulated under the cogni

30、zance of the JC- 16 Committee on Interface Technology.) 1 Scope This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL-2 logic switching range, nominally O V to 2.5 V. The standard may be applied to ICs operating with separa

31、te VDD and VDDQ supply voltages. In many cases VDD and VDDQ will have the same voltage level. The VDD value is not specified in this standard other than that VDDQ value may not exceed that of VDD. 1.1 Standard structure The standard is defined in three clauses: The first clause defines pertinent sup

32、ply voltage requirements common to all compliant ICs. The second clause defines the minimum dc and ac input parametric requirements and ac test conditions for inputs on compliant devices. The third clause specifies the minimum required output characteristics of, and ac test conditions for, compliant

33、 outputs targeted for various application environments. The output specifications are divided into two classes, Class I and Class II, which are distinguished by drive requirements and application. A given IC need not be equipped with both classes of output drivers, but each must support at least one

34、 to claim SSTL-2 output compliance. The full input reference level (VREF) range specified is required on each IC in order to allow any SSTL-2 IC to receive signals from any SSTL-2 output driver. 1.2 Rationale and assumptions This standard has been developed particularly with the objective of providi

35、ng a relatively simple upgrade path from MOS push-pull interface designs. The standard is particularly intended to improve operation in situations where busses must be isolated from relatively large stubs. External resistors provide this isolation and also reduce the on-chip power dissipation of the

36、 drivers. Busses may be terminated by resistors to an external termination voltage. JEDEC Standard No. 8-9B Page 2 1 Scope (contd) 1.2 Rationale and assumptions (contd) Actual selection of the resistor values is a system design decision and beyond the scope of this standard. However in order to prov

37、ide a basis, the driver characteristics will be derived in terms of a typical 50 i2 environment. While driver characteristics are derived from a 50 i2 environment, this standard will work for other impedance levels. The system designer will be able to vary impedance levels, termination resistors and

38、 supply voltage and be able to calculate the effect on system voltage margins. This is accomplished precisely because drivers and receivers are specified independently of each other. The standard defines a reference voltage VF which is used at the receivers as well as a voltage VTT to which terminat

39、ion resistors are connected. In typical applications VTT tracks as a ratio of VDDQ. In turn VF will be given the value of VTT. In some standards this ratio equals 0.5. 2 Supply voltage and logic input levels The standard defines both ac and dc input signal values. Making this distinction is importan

40、t for the design of high gain, differential, receivers that are required. The ac values are chosen to indicate the levels at which the receiver must meet its timing specifications. The dc values are chosen such that the final logic state is unambiguously defined, that is once the receiver input has

41、crossed this value, the receiver will change to and maintain the new logic state. The reason for this approach is that many input wave-forms will include a certain amount of “ringing”. The system designer can be sure that the device will switch state a certain amount of time after the input has cros

42、sed ac threshold and not switch back as long as the input stays beyond the dc threshold. The relationship of the different levels is shown in figure 1. An example of ringing is illustrated in the dotted wave-form. I R I/ VIH(ac) IV VI H (d c) . I VIL(ac) VREF VIL(dc) vss Figure 1 - SSTL-2 input volt

43、age levels JEDEC Standard No. 8-9B Page 3 Symbol 2 Supply voltage and logic input levels (contd) 2.1 Supply voltage levels Parameter Min. Max. Units Notes Table 1 - Supply voltage levels VIH(dc) VIL(dc) NOTE 1 There is no specific device VDD supply voltage requirement for SSTL-2 compliance. However

44、under all conditions VDDQ must be less than or equal to VDD. dc input logic high VF + 0.15 VDDQ + 0.3 V 1 dc input logic low - 0.3 VREF - O. 15 V 1 NOTE 2 The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be (0.49-

45、0.51) x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. NOTE 3 Peak to peak ac noise on VREF may not exceed +/-2% of NOTE 4 VTT of transmitting device must track VREF of receiving device. 2.2 Input parametric Table 2a - Input dc logic levels NOTE 1 Within this stand

46、ard, it is the relationship of the VDDQ of the driving device and the VREF of the receiving device that determines noise margins. However, in the case of VIHmax,) (i.e. input overdrive) it is the VDD of the receiving device that is referenced. In the case where a device is implemented that supports

47、SSTL-2 inputs but has no SSTL-2 outputs (e.g., a translator), and therefore no VDDQ supply voltage connection, inputs must tolerate input overdrive to 3.0 V (High corner VDDQ + 300 mV). JEDEC Standard No. 8-9B Page 4 Symbol 2 Supply voltage and logic input levels (contd) 2.2 Input parametric (contd)

48、 Table 2b - Input ac logic levels Parame ter Min. Max. Units Notes VIH(ac) VIL(ac) ac input logic high VREF + 0.3 1 V ac input logic low VREF - 0.3 1 V 2.3 AC test conditions Symbol VREF VswmhaX The ac input test conditions are specified to be able to obtain reliable, reproducible test results in an

49、 automated test environment, where a relatively high noise environment makes it difficult to create clean signals with limited swing. The tester may therefore supply signals with a 1.5 V peak to peak swing to drive the receiving device. Note however, that all timing specifications are still set relative to the ac input level. This is illustrated in figure 2. Condition Value Units Notes Input reference voltage 0.5 x VDDQ V 124 Input signal maximum peak to peak swing 1.5 V 12 Table 3 - AC input test conditions I SLEW I Input signal minimum slew rate I 1.0 I vns I 3 I NOTE 1