JEDEC JESD28-A-2001 Procedure for Measuring N-Channel MOSFET Hot-Carrier-Induced Degradation under DC Stress《测量DC压力下最大基层电流N-信道MOSFET Hot-Carrier-Induced降级》.pdf

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1、JEDEC STANDARD Procedure for Measuring N-Channel MOSFET Hot-Carrier-Induced Degradation Under DC Stress JESD28-A (Revision of JESD28) DECEMBER 2001 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION Electronic Industries Alliance NOTICE JEDEC standards and publications contain material that has been prepared,

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9、ted in the U.S.A. All rights reserved JEDEC Standard No. 28-A A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER- INDUCED DEGRADATION UNDER DC STRESS CONTENTS Page Introduction ii 1 Scope 1 2 Applicable standards 1 3 Terms and definitions 2 4 Technical requirements 4.1 Equipment requirements 4.2

10、 Test structure requirements 4.3 Measurement requirements 5 Hot carrier stress test procedure 5.1 Determining stress bias conditions 5.2 Selecting test devices 5.3 Initial characterization 5.4 Stress cycle 5.5 Interim characterization 5.6 Stress termination 6 Data analysis 8 7 Precautions 7.1 Test s

11、ample 7.2 Stress 7.3 Interim measurements 7.4 Data analysis 8 Required reporting 8.1 Test transistor identification 8.2 VDD, VBB 8.3 MOSFET channel length and width 8.4 VDS at stress, VBs at stress, VGS at stress 8.5 Initial IB at stress 8.6 Initial ID(Ln), gm(mx), VT(ci), VT(ext), ID(sat) 8.8 Total

12、 test time 8.9 Measurement temperature 8.7 tTAR for ID(Ln), gm(mx), VT(ci), VT(ext), ID(sat) 9 9 9 9 10 10 10 10 10 10 10 11 11 11 11 -1- JEDEC Standard No. 28-A A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER- INDUCED DEGRADATION UNDER DC STRESS Introduction Hot-carrier-induced degradation o

13、f MOSFET parameters over time is an important reliability concern in modern microcircuits. High energy carriers, also called hot carriers, are generated in the MOSFET by the large channel electric fields near the drain region. The electric fields accelerate the carriers to effective temperatures wel

14、l above the lattice temperature. These hot carriers transfer energy to the lattice through phonon emission and break bonds at the Si/SiO2 interface. Carriers also are injected into the Si02 and can be trapped there. The trapping or bond breaking creates oxide charge and interface traps that affect t

15、he channel carrier mobility and the effective channel potential. Interface traps and oxide charge affect transistor performance in all operating regimes. Parameters such as threshold voltage, transconductance, and drive currents are commonly monitored to identify performance change. The rate of chan

16、ge of each parameter is determined by the MOSFET design and IC process details. Both p and n-channel MOSFETs are affected by hot carriers. This document addresses only n-channel MOSFETs. -11- JEDEC Standard No. 28-A Page 1 A PROCEDURE FOR MEASURING N-CHANNEL MOSFET HOT-CARRIER- INDUCED DEGRADATION U

17、NDER DC STRESS (From JEDEC Board Ballot JCB-O 1-48, formulated under the cognizance of the JC- 14.2, Hot Carrier Working Group.) 1 Scope This document describes an accelerated test for measuring the hot-carrier-induced degradation of a single n-channel MOSFET using dc bias. The purpose of this docum

18、ent is to specify a minimum set of measurements so that valid comparisons can be made between different technologies, IC processes, and process variations in a simple, consistent and controlled way. The measurements specified should be viewed as a starting point in the characterization and benchmark

19、ing of the transistor manufacturing process. In this document, degradation criteria are specified. However, these are to be used for comparison purposes only and should not be used as acceptance or rejection criteria. It is also important to realize that this procedure should not be interpreted as a

20、 means of predicting MOS IC failure rates. The impact of the n-channel MOSFET degradation on actual circuit performance is not addressed in this document. Though this procedure was developed for wafer level stressing, it is also applicable to packaged structures. The material contained in this publi

21、cation was formulated under the cognizance of the JEDEC JC-14.2 Committee. 2 Applicable standards ASTM F6 16-86, Standard Method for Measuring MOSFET Drain Leakage Current ASTM F6 17-86, Standard Method for Measuring MOSFET Linear Threshold Voltage ASTM F1096-87, Standard Method for Measuring MOSFET

22、 Saturated Threshold Voltage JESD77-A, Terms, Definitions, and Letter Symbols for Discrete Semiconductor and Optoelectronic Devices JESDGO, A Procedure for Measuring P-Channel MOSFET Hot-Carrier-Induced Degradation Under DC Stress JEDEC Standard No. 28-A Page 2 3 Terms and definitions 3.1 Metal oxid

23、e semiconductor field effect transistor (MOSFET): An insulated-gate, field- effect transistor in which the insulating layer between each gate electrode and the channel is oxide material; the gate is metal or another highly conductive material. NOTE See JESD77-B for further clarification of MOSFET te

24、rms. 3.2 drain voltage (VDS): The dc drain-source voltage. 3.3 gate voltage (VGS): The dc gate-source voltage. 3.4 bulk voltage (VBS): The dc bulk-source voltage. 3.5 drain current (ID): The direct current into the drain contact. 3.6 bulk current (IB): The direct current into the bulk contact. 3.7 f

25、orward mode: The mode in which the drain to source polarity during test is the same as that during the application of stress. 3.8 nominal power supply voltage (VDD): The nominal drain supply voltage of the technology. 3.9 nominal bulk supply voltage (VBB): The nominal bulk voltage of the technology.

26、 3.10 linear drain voltage (VDSGn): The dc drain-source voltage for hear region measurements. NOTE Typically, VDS(I) is 100 mV for VDD = 5 V. 3.11 linear drain current (IDGn): The dc drain current measured when the transistor is biased in the linear region. NOTE Typical dc bias voltages for ID(I) me

27、asurements are VDS = O. 1 V, VGS = VDD, VBS = VBB. 3.12 maximum linear transconductance (gm(max): The maximum slope of the ID-VGS curve in the linear region. The gate voltage shall be varied in increments no greater than 0.02 V from below the turn-on voltage to a value great enough to ensure that th

28、e maximum slope point has been reached. The slope shall be calculated using a three-point linear least squares best fit algorithm as defined in ASTM F6 17-86 standard. NOTE Typical dc bias voltages for gmx) measurements are VDS = VDS(L), VBS = VBB. JEDEC Standard No. 28-A Page 3 3 Terms and definiti

29、ons (contd) 3.13 constant current threshold voltage (VT(ci): The constant current threshold voltage is defined as ID = O. lpA - L VT(ci) is the gate voltage applied to the device at which the drain current is equal to O. 1 pA times the ratio of gate width (W) to gate length (L). W and L are the gate

30、 width and gate length as printed on the wafer. NOTE 1 size is larger than 1 mV, then a linear interpolation method may be used to achieve the 1 mV resolution. The measurement technique must determine VT(ci) to within a 1 mV resolution. If the VGS step NOTE 2 Typical dc bias voltages for VT(ci) meas

31、urements are VDs = VDs(hn), VBS = VBB for linear region measurment, or VDs = vDs(sat), VBs = VBB for saturation region measument. 3.14 extrapolated threshold voltage (vT( i.e. terminals shall not be floating. To minimize parasitic voltage drops between the applied drain stress voltage and the device

32、, the resistance from the probe pads to the device source, drain, and substrate should be minimized. 4.3 Measurement requirements The device should be set up at the wafer level on a probe station providing a stable platform via a vacuum chuck or as a packaged part in a test fixture. Once set, this t

33、emperature must be maintained to within +/- 2.0 “C of this set point for the duration of the measurement. At the end of each hot carrier stress interval, the stress is terminated and device parameters are measured. The stress time interval should be known to an accuracy of +/- 1%. JEDEC Standard No.

34、 28-A Page 5 Stress Cycle 1 d/ Interim Characterization Record Data 5 Hot carrier stress test procedures Increment Stress Timer Figure 1 describes the hot carrier stress test procedure. 1 Termination? I I Stop Test I Figure 1 - The hot carrier stress test procedure Initial tests are used to select a

35、 “good” device (see 5.2) and to determine initial unstressed parameter values. If the device is determined to be “good” data is recorded and the stress cycle begins. During the stress cycle the device is biased using the selected stress bias condition. Since parameter degradations typically exhibit

36、a power-law behavior the recommended stress intervals are 1/2 decade time-steps (see 5.4). After each stress cycle the device parameters are again determined, recorded and compared to the initial values. If the parameter degradation exceeds the termination criteria (see 5.6), testing ends. Otherwise

37、, another stress cycle is initiated. The sections below describe in greater detail the hot carrier stress algorithm. JEDEC Standard No. 28-A Page 6 5 Hot carrier stress test procedures (contd) 5.1 Determining stress bias conditions Hot carrier stressing should be performed under constant voltage bia

38、s conditions at the temperature specified in 4.3. To determine the drain stress voltage, the ID-VDS curves for the device must be examined. Examples of ID-VDs characteristic curves for an n-channel MOSFET are shown in Figure 2. 0.025 0.02 h 0.015 6 - 0.01 W ci 0.005 O O 2 4 6 8 10 Figure 2 - N-chann

39、el MOSFET drain current characteristics The drain current is plotted as a function of drain voltage at three different gate bias conditions. The linear, saturation, and breakdown regions are shown on the plot. Transistor breakdown, whether due to drain avalanching, punchthrough, or bipolar snapback,

40、 determines the maximum VDS stress limit. The maximum Vds stress limit should be deterimined at the Vgs which produces the worst case degradation. The minimum realistic drain stress bias is restricted by long test times or by inaccurate extrapolations to tTAR. Maximum stress conditions should be set

41、 to minimize activating any effect that is not seen at the operating conditions. For a given selected drain bias condition, the corresponding gate bias should be set to induce the maximum possible degradation. Operating conditions of the device should be taken into account when setting the gate bias

42、 voltage. Peak IB gate biasing may produce the greatest rate of n-channel MOSFET degradation, but this should be verified for each technology. A series of hot carrier tests at a fixed Vds and at least 5 Vgs values can be used to estimate the peak degradation. JEDEC Standard No. 28-A Page 7 5 Hot car

43、rier stress test procedures (contd) 5.2 Test devices A transistor with gate, drain, and source leakage currents that meet the requirements of the process shall be used. Transistors used for drain breakdown, peak IB measurements, or for any other test that use bias voltages greater than nominal opera

44、ting conditions shall not be used for hot carrier stress testing. 5.3 Initial characterization Monitored parameters shall include VT(ci), VT(ext), gm(max), ID(lin), and ID(sat) all in the forward mode. The parameters shall be recorded, as these will be used for determining parametric shifts. Other p

45、arameters may also be measured. 5.4 Stress cycle The transistor will be stressed with the voltages determined in 5.1. The voltages shall be applied in the following order: VBS first, VGS second, and VDS last. The stress begins when VDS has been applied. The stress continues until a stress time inter

46、val has been reached. Turning off the bias shall be done in the reverse order, with VDS first, VGS second, and VBS last. Since the typical degradation follows a power-law with time, the recommended stress intervals are 1/2 decade time-steps. For example, the cumulative stress times could be 10, 30,

47、100, 300, 1000,3000, 10000,30000, and 100000 seconds. In this example, the device would be stressed for 1 O seconds. After this stress interval, the device parameters are measured. The device would then be stressed for 20 additional seconds and the parameters again measured. The next stress interval

48、 would be 70 seconds. This procedure continues until stress termination occurs. 5.5 Interim characterization The five parameters that shall be measured and recorded are VT(ci), VT(ext), gm(max), ID(1in) and ID(sat). Other parameters may also be measured. 5.6 Stress termination Each device shall be s

49、tressed until at least one parameter reaches or exceeds the specified target value (see 3.16), or two time decades of valid data have been taken (see 7.4). JEDEC Standard No. 28-A Page 8 6 Data analysis The percent change values are calculated from: where: P(0) is the initial parameter value. P(t) is the parameter value at time t. The absolute value of the change in each parameter shall be fitted to the following equation using a least-squares fit: lY(t)l = Ct“ (4) where: IYt)l is the absolute value change in the parameter. t is the cumulative stress time. For each parameter analy