JEDEC JES2-1992 Transistor Gallium Arsenide Power Fet Generic Specification《电晶体 砷化镓场效应晶体管 总规范》.pdf

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1、. EIA JES2 92 m 3234b00 0502039 738 m JEDEC SPEC1 FICATION Transistor, Gallium Arsenide Power Fet, Generic Specification JES2 JULY 1992 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JES2 i2 3234600 050204

2、0 45T NOTICE JEDEC Standards and Publications contain material that has been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. JEDEC Standards and Publications are designed to serve the public interest th

3、rough eliminating misunderstandings between manufacturers and purchases, facilitating interchangeability and improvement of products, and assisting the purchaser is selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards shall not in any res

4、pect preclude any member or nonmember of JEDEC from manufacturing or selling products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members, whether the standard is to be used either domestically or internationally. J

5、EDEC Standards and Publications are adopted without regard to whether their adoption may involve patents or articles, materials, or processes. By such action, JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC Standards o

6、r Publications. The information included in JEDEC Standards and Publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC Standard or Publicatio

7、n may be further processed and ultimately became an EIA Standard. Inquiries, comments, and suggestions relative to the content of this JEDEC Specifcation should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2001 Pennsylvania Ave., N.W., Washington, D.C. 2ooo6. Published by ELECT

8、RONIC INDUSTRIES ASSOCIATION Engineering Department 2001 Pennsylvania Ave., N.W. Washington, D.C. 2ooo6 PRICE: Please refer to the current Catalog of EIA consequently portions of the specification may not be applicable to unpackaged and unmounted chips. The intent of this specification is to serve a

9、s a guideline for transistor manufacturers and users (purchasers) to use in the development of their own specifications for power GaAs FETs for applications requiring high reliability. The specific applications and device designs will define the values for parameters left undefined in this specifica

10、tion. 0 It is expected that the manufacturer, prior to acceptance of this specification, will have generated reliability data which indicate to the purchaser that they can fulfill the reliability goals of the specification and can identifi, the most probable failure mechanism. 1.2 Part Number The co

11、mplete part number shall be as follows: I Device Type Specification Number COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JES2 92 3234600 0502047 04 JEDEC Specilkation No. 2 Page 2 The device type and package or chip-carrier outline shall be as follows: 1.2.1 De

12、vice lhe and Package or ChiD-Caxrier - Outline pevice TM) e Package o r ChiD-Cam er Outline xx Figure 1 1.3 The device shall have the maximum rating at TA = 25 Weldable for Electronic Component Parts MIL-STD- 1285 Marking of Electrical and Electronic Parts MIL-STD- 1547 Parts, Materials, and Process

13、es for Space and Launch Vehicles MIL-STD-45662 Calibration Systems Requirements APPENDICES 1 Test Procedure for RF Power, Gain, Efficiency and Impedance COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JES2 92 m 3234600 0502049 b7 W JEDEC Specification No. 2 Page

14、4 3. REQUIREMENTS 3.1 Genera Devices supplied to this Specification shail meet the requirements as specified herein. Depending on the application the device may be mounted in hermetic packages or unsealed chip-carriers. 3.2 The design, construction, and physical dimensions shall be as specified here

15、in. wn. Constructio n. and Phvsical Dimensi= 3.2.1 package - IC hiD Cam er1 Outline The package (chip carrier) outline shall be as specified in Figure 1. 3.2.2 Hermetic Package The package design must have been quaifed as hermetic for space applications, e.g., metal-ceramic construction is qualifed.

16、 3.2.3 ChiD Cam ers Chip carriers may be required for mounting higher frequency devices. Such carriers are intended for use only in hermeticaily sealed circuits. 3.2.3.1 Chip Carrier Constructioq Chip carriers may be constructed of a combination of metailized ceramic and metal to provide a mounting

17、surface for the device and a thermal path for heat dissipation. Metal parts and metallized surfaces shail be gold plated (50 to 100 micro-inches) over nickel plate per MIL-G-45204. 3.3 Materials 3.3.1 Substrate Q ualitv Gallium arsenide substrates used in the production of the devices shail meet or

18、exceed a minimum specification for quality. The specification on substrate quality prepared by the manufacturer, and any proposed change to the specification, must be approved by the purchaser. The results of tests on the substrates shall be available for examination by the purchaser. 3.3.2 External

19、 Metal Surfaces External metai surfaces shail be plated with 50 to 100 microinches of gold except that ends of leads may be unplated. 3.3.3 (application related guideline) Minimal use of magnetic materials in the construction of the GaAs FET should be considered to prevent magnetic interference with

20、 surrounding experiments and circuits. 3.3.4 The microstrip substrates and lumped element capacitors or resistors used in the production of matching or combining circuits internal to the device package or chip carrier shall meet or exceed a minimum specification for quality. These Matchine or Combin

21、ing Circuit ComDonents COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JES2 92 m 3234b00 0502050 3T m JEDEC Specification No. 2 Page 5 specifications, prepared by the manufacturer, and any proposed change to the specifications must be approved by the purchaser. T

22、he results of tests on the subject parts shall be available for examination by the purchaser. Any metallization where die bonding or wire bonding is to be performed on the substrates or lumped element capacitors shall be gold. Any metal wires, ribbons or foils used for inductances or circuit interco

23、nnection shall be gold. 3.3.5 Fungus - Resistance External materials used in the construction of the device shall be non-nutrient to fimgus. 3.4 Wafer Lot Control AU parts supplied to the requirements of this specification shall be: (1) from a single wafer, or (2) from wafers from the same wafer lot

24、, or (3) fiom a minimum number of lots (in the order of preference shown). Each wafer lot shall be assigned a unique identifier that provides traceability to ail processing steps. If the wafer lot consists of more than one wafer, the wafers within the lot shall be processed in a manner that requires

25、 every wafer to be subjected to each and every process step as a group through metal and dielectric deposition, etching, and anneaing processes. A lot shaii consist of devices originating from a given group of wafers from a common ingot and processed (under equivalent expitaxial or ion implantation

26、conditions) in the same epitaxial growth or ion implantation run. 3.4.1 Wafer ACCeDtanCe InsDection Each wafer designated for devices supplied to this specification shall conform to the requirements of paragraph 4.4. a 3.5 Surface Passivation or Protection The device shall be glassivated to preclude

27、 particles undetected by the PIND test from causing an internal short. 3.6 Surface Metallization The top surface of the die-metallization shall be gold with gold wire, ribbon, or foil attachments between the die and package or internal circuitry terminals. This does not preclude the use of aluminum

28、for the gate metallization if the manufacturer can demonstrate the quality, uniformity, and reliability of their banier metal system per MIL-STD-1547, Section 1400. 3.7 Electrical Characteristics and Ratings 3.7.1 Ratines The ratings shaii be as specified in paragraph 1.3. 3.7.2 Electrical Characten

29、stice The electrical characteristics shall be as specified in Table I. The RF electrical characteristics are to be measured as indicated in Appendix 1. Unless otherwise noted, the mounting fixture temperature shall be TBDCf30C. COPYRIGHT Electronic Industries AllianceLicensed by Information Handling

30、 ServicesEIA JESZ! 92 M 3234600 0502051 235 M JEDEC Specification No. 2 Page 6 3.8 Process Conditioning, Testing and Screening All devices shall be subjected to the process-conditioning, testing, and screening as specified in Table II. 3.9 Qualification Devices supplied to this specification shall b

31、e a product which has been tested and passed the qualification tests specified herein. 3.10 Devices supplied to this specification shall be a product which has passed lot quality conformance as specifed in Table V. t Qualitv Co n formance 3.11 Traceability A device supplied to this specification sha

32、ll be traceable to a given wafer, wafer position in a given implantation or epitaxial run and wafer position in a given crystal ingot. The device package or chip carrier shall also be traceable through the various processing steps back to the original package production lot. Device lots shall confor

33、m to the requirements of paragraph 4.3. 3.12 Serialization Each item shall be assigned a serial number that identifies the wafer from which the part was obtained and uniquely identifies the part from ail other parts assembled within the lot. 3.13 Marking Making shail be in accordance with MIL-STD-12

34、85 and shail consist of the follomg items (where size or other design considerations will not allow full marking of part, marking for each part shall be in accordance with the following precedence): a. PartNumber b. Serial Number/Lot Code c. Date Code d. Manufacturers Name or Symbol Configuration or

35、 polarity of.leads must always be indicated either by package m.-xk.ing or variation in lead geometry for the various leads. 3.13.1 arkina Permanence Marking shall remain legible after brushing when the device is subjected to tests of MIL-STD-202, Method 2 15. 3.13.2 l2aw22 monitor wafer acceptance,

36、 screening and qualification tests: witness fmal tests: and review data from process- conditioning, testing, screening, and qualification. The manufacturer shail not the purchaser at least 5 working days prior to the start of wafer acceptance, internal visual inspections, final test, and qualificati

37、on. 4.9 Test and InsDection Da Each shipment of devices shail include a report that, as a minimum, includes the following information for qualification (if qualification is done) or developmental device shipments: a. b. Certificate of conformance to the contents of this specification. Type and numbe

38、r of parts tested. c. Record of and number of failures and failure modes at initial electrical (except no failure analysis on devices failing the manufacturers dc go-no go test before the initial electrical measurement), final electrical, qualification and lot quality conformance measurements. d. Re

39、corded values of all measured parameters, including burn- in deltas, referenced to device serial number. e. Failure analysis report on devices failing electrically after pre- burn-in electrical test per Table II. f. Radiographs referenced to part serial number. COPYRIGHT Electronic Industries Allian

40、ceLicensed by Information Handling ServicesEIA JES2 92 3234600 O502060 2Y8 JEDEC Specification No. 2 Page 15 g. SEM inspection results including photographs. h. Full report of qualification including test sequence, number of parts tested, number accepted, and recorded values of measured parameter re

41、ferenced to the part serial number. For non-qualification device shipments, only items a, b, d, e, fand a statement indicating the initial number of devices in the lot plus the number of failures need be included. 4.9.1 Certification The manufacturer shall certify that the material meets aU the requ

42、irements of this specification and the purchase order. The certification shall include the following information as a minimum: Title: Test Data for (Complete Part No.) Purchase Orders: (Number of all applicable) Manufacturer: (Manufacturers name and address) Period of Test: (Dates started and dates

43、completed) Lot Numbers: (Wafer lot/date code) Date: (Date of documentation formation) Name and Signature: (Name, title and signature of the quaiity control manager or his designated representative) 4.10 Notification of Changes No change shall be made to the items listed below which affect the quaiit

44、y, reliability and electrical interchangeability of the device without written notification and approval of the purchaser. a. Design b. Configuration c. Materials d. Manufacturer 4.11 Incoming InsDection The manufacturer shall perform pertinent incoming inspection of vendor- supplied component parts

45、 to insure uniformity and quality of the parts. Details of the incoming inspection will be outlined in manufacturers detailed subspecifications to this specacation. a COPYRIGHT Electronic Industries AllianceLicensed by Information Handling ServicesEIA JESZ 92 D 3234600 05020b1 184 D JEDEC Specificat

46、ion No. 2 Page 16 4.12 Measurements 4.12.1 Eauinment C heckout characteristics of electrical test equipment prior to each usage, in accordance with MIL-S-19500, paragraph 4.3.1.5. The manufacturer shall ver the measurement/operation 4.12.2 muioment Cai ibration The manufacturer shall establish and m

47、aintain a program for calibration, control and maintenance of measuring and test equipment in accordance with MIL-STD-750, paragraph 4.1.4. 5. PREPARATION FOR DELIVERY 5.1 Devices shall be prepared for delivery with preservation, packaging, and packing in accordance with MIL-S-19491. The devices sha

48、ll be packaged to prevent damage during transit. eservation - Packain and Packing 5.1.1 Marking of the package and unit container shall be in accordance with MIL- STD-129 and shall consist of the following: a. Purchase order b. Part number (per para. 1.2) c. Inspection lot identification code d. Man

49、ufacturers name or symbol Packge and U nit Container Marking 5.1.2 Qualification Samdes Qualificaum test samples shall be packaged separa,zly and in addition to the marking above, each unit container shall be clearly marked with the following as applicable: QUALIFICATION TEST SAMPLES NO“ FOR FLIGHT USE 5.2 Electrostatic and Environmental Protection The devices shall be protected from electrostatic damage by enclosing each device in the initiai wrap or bag fabricated from barrier materiai conforming to the requirements of MIL-S-19491. In addition, the devicesshall be in