ETSI TR 103 570-2017 CYBER Quantum-Safe Key Exchanges (V1 1 1).pdf
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1、 ETSI TR 103 570 V1.1.1 (2017-10) CYBER; Quantum-Safe Key Exchanges TECHNICAL REPORT ETSI ETSI TR 103 570 V1.1.1 (2017-10) 2 Reference DTR/CYBER-QSC-007 Keywords algorithm, confidentiality, quantum cryptography, security ETSI 650 Route des Lucioles F-06921 Sophia Antipolis Cedex - FRANCE Tel.: +33 4
2、 92 94 42 00 Fax: +33 4 93 65 47 16 Siret N 348 623 562 00017 - NAF 742 C Association but non lucratif enregistre la Sous-Prfecture de Grasse (06) N 7803/88 Important notice The present document can be downloaded from: http:/www.etsi.org/standards-search The present document may be made available in
3、 electronic versions and/or in print. The content of any electronic and/or print versions of the present document shall not be modified without the prior written authorization of ETSI. In case of any existing or perceived difference in contents between such versions and/or in print, the only prevail
4、ing document is the print of the Portable Document Format (PDF) version kept on a specific network drive within ETSI Secretariat. Users of the present document should be aware that the document may be subject to revision or change of status. Information on the current status of this and other ETSI d
5、ocuments is available at https:/portal.etsi.org/TB/ETSIDeliverableStatus.aspx If you find errors in the present document, please send your comment to one of the following services: https:/portal.etsi.org/People/CommiteeSupportStaff.aspx Copyright Notification No part may be reproduced or utilized in
6、 any form or by any means, electronic or mechanical, including photocopying and microfilm except as authorized by written permission of ETSI. The content of the PDF version shall not be modified without the written authorization of ETSI. The copyright and the foregoing restriction extend to reproduc
7、tion in all media. ETSI 2017. All rights reserved. DECTTM, PLUGTESTSTM, UMTSTMand the ETSI logo are trademarks of ETSI registered for the benefit of its Members. 3GPPTM and LTE are trademarks of ETSI registered for the benefit of its Members and of the 3GPP Organizational Partners. oneM2M logo is pr
8、otected for the benefit of its Members. GSM and the GSM logo are trademarks registered and owned by the GSM Association. ETSI ETSI TR 103 570 V1.1.1 (2017-10) 3 Contents Intellectual Property Rights 6g3Foreword . 6g3Modal verbs terminology 6g31 Scope 7g32 References 7g32.1 Normative references . 7g3
9、2.2 Informative references 7g33 Abbreviations . 13g34 Quantum-safe key exchanges . 13g34.1 Introduction 13g34.2 Use cases 14g34.2.1 General comments 14g34.2.2 Network security. 14g34.2.3 Internet of Things . 14g34.3 Candidate primitives. 14g35 Implementation considerations . 15g35.1 Introduction 15g
10、35.2 Active security 15g35.2.1 Invalid key attacks 15g35.2.2 Key validation . 15g35.2.3 Performance impact 16g35.3 Side-channel protection 16g35.3.1 Side-channel vulnerabilities 16g35.3.2 Side-channel mitigations . 16g35.3.3 Performance impact 16g36 Learning with Errors 17g36.1 Introduction 17g36.2
11、LWE key exchange 17g36.2.1 Overview 17g36.2.2 Public parameters 18g36.2.3 Key generation 18g36.2.4 Key extraction . 18g36.2.5 Reconciliation . 19g36.3 Ring-LWE key exchange . 19g36.3.1 Overview 19g36.3.2 Public parameters 20g36.3.3 Key generation 21g36.3.4 Key extraction . 21g36.3.5 Reconciliation .
12、 21g36.4 Implementation considerations . 22g36.4.1 Active security 22g36.4.2 Side-channel protection 22g36.5 Parameter selection. 22g36.5.1 LWE proposed parameters 22g36.5.2 Ring-LWE proposed parameters . 23g36.5.3 Security estimates . 23g36.6 Performance . 23g36.6.1 Performance on a 64-bit processo
13、r . 23g36.6.2 Performance on a 32-bit embedded processor 24g36.6.3 Performance on 32-bit microcontrollers . 24g36.7 Summary 25g37 Supersingular isogenies 25g3ETSI ETSI TR 103 570 V1.1.1 (2017-10) 4 7.1 Introduction 25g37.2 SIDH key exchange 25g37.2.1 Overview 25g37.2.2 Public parameters 26g37.2.3 Ke
14、y generation 26g37.2.4 Key exchange 27g37.3 Implementation considerations . 27g37.3.1 Static key exchanges . 27g37.3.2 Side-channel protection 28g37.4 Parameter selection. 28g37.4.1 Proposed parameters . 28g37.4.2 Security estimates . 28g37.5 Performance . 28g37.5.1 Performance on a 64-bit desktop p
15、rocessor 28g37.5.2 Performance on a 64-bit embedded processor 29g37.5.3 Performance on a 32-bit embedded processor 29g37.6 Summary 29g38 Key exchanges from key transport mechanisms 29g38.1 General construction. 29g38.2 Niederreiter. 30g38.2.1 Introduction. 30g38.2.2 Niederreiter key exchange 30g38.2
16、.2.1 Overview . 30g38.2.2.2 Public parameters 31g38.2.2.3 Key generation 31g38.2.2.4 Decryption . 32g38.2.3 Implementation considerations . 32g38.2.3.1 Active attacks 32g38.2.3.2 Side-channel attacks 32g38.2.4 Parameter selection . 32g38.2.4.1 Proposed parameters . 32g38.2.4.2 Security estimates . 3
17、3g38.2.5 Performance 33g38.2.5.1 Performance on a 64-bit server processor . 33g38.2.5.2 Performance on a 64-bit desktop processor 33g38.2.5.3 Performance on an 8-bit microcontroller 33g38.2.6 Summary . 34g38.3 NTRU . 34g38.3.1 Introduction. 34g38.3.2 NTRU key exchange . 34g38.3.2.1 Overview . 34g38.
18、3.2.2 Public parameters 35g38.3.2.3 Decryption . 35g38.3.3 Implementation considerations . 35g38.3.3.1 Static key exchange . 35g38.3.3.2 Side channel attacks 35g38.3.4 Parameter selection . 36g38.3.4.1 Proposed parameters . 36g38.3.4.2 Security estimates . 36g38.3.5 Performance 36g38.3.5.1 Performan
19、ce on a 64-bit desktop processor 36g38.3.5.2 Performance on a 32-bit embedded processor. 36g38.3.5.3 Performance on a 32-bit microcontroller 37g38.3.6 Summary . 37g39 Conclusions 37g3Annex A: LWE design and security considerations 39g3A.1 LWE and Ring-LWE variants 39g3A.1.1 Rings 39g3A.1.2 Distribut
20、ions . 39g3ETSI ETSI TR 103 570 V1.1.1 (2017-10) 5 A.1.2.1 Discrete Gaussians 39g3A.1.2.2 Approximate Gaussians 39g3A.1.2.3 Small distributions 40g3A.1.2.4 Learning with Rounding . 40g3A.1.3 Varying g4 . 40g3A.1.4 Reconciliation mechanisms 41g3A.1.5 Key transport 41g3A.2 Security considerations. 42g
21、3A.2.1 Provable security 42g3A.2.2 Passive security 42g3A.2.3 Active security 43g3Annex B: SIDH background and security considerations 44g3B.1 Mathematical background 44g3B.1.1 Isogenies . 44g3B.1.2 Parameter generation 44g3B.1.3 Public key compression 45g3B.2 Security. 45g3B.2.1 Provable security 4
22、5g3B.2.2 Passive security 46g3B.2.3 Active security 46g3Annex C: Open Quantum-Safe benchmarks . 48g3C.1 Open Quantum-Safe . 48g3C.2 Benchmarks 48g3C.2.1 Performance on a 64-bit desktop processor 48g3C.2.2 Performance on a 64-bit laptop processor 49g3C.2.3 Performance on a 32-bit embedded processor 4
23、9g3C.3 Discussion 49g3History 50g3ETSI ETSI TR 103 570 V1.1.1 (2017-10) 6 Intellectual Property Rights Essential patents IPRs essential or potentially essential to the present document may have been declared to ETSI. The information pertaining to these essential IPRs, if any, is publicly available f
24、or ETSI members and non-members, and can be found in ETSI SR 000 314: “Intellectual Property Rights (IPRs); Essential, or potentially Essential, IPRs notified to ETSI in respect of ETSI standards“, which is available from the ETSI Secretariat. Latest updates are available on the ETSI Web server (htt
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