DLA SMD-5962-99570 REV B-2002 MICROCIRCUIT DIGITAL-LINEAR 12 BIT 8 CHANNEL SERIAL A D CONVERTER MONOLITHIC SILICON《微型电路 数字线型 12位8通道 系列A D转换器 单块硅》.pdf

《DLA SMD-5962-99570 REV B-2002 MICROCIRCUIT DIGITAL-LINEAR 12 BIT 8 CHANNEL SERIAL A D CONVERTER MONOLITHIC SILICON《微型电路 数字线型 12位8通道 系列A D转换器 单块硅》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-99570 REV B-2002 MICROCIRCUIT DIGITAL-LINEAR 12 BIT 8 CHANNEL SERIAL A D CONVERTER MONOLITHIC SILICON《微型电路 数字线型 12位8通道 系列A D转换器 单块硅》.pdf（28页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. gt 02-06-20 R. Monnin B Changes to paragraph 1.4, table I, and figure 3. - gt 02-09-06 R. Monnin REV SHET REV B B B B B B B B B B B B B SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 REV STATUS REV B

2、 B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rajesh Pithadia DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Rajesh Pithadia COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AP

3、PROVED BY Raymond Monnin MICROCIRCUIT, DIGITAL-LINEAR, 12 BIT, 8 CHANNEL, SERIAL A/D CONVERTER, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 99-12-16 MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-99570 SHEET 1 OF 27 DSCC FORM 2233 APR 97 5962-E541-02 DIS

4、TRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99570 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SH

5、EET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identif

6、ying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 99570 01 Q R X Federal stock class designator RHA designator (see 1.2.1) Devicetype (see 1.2.2) Device class designator Cas

7、eoutline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, append

8、ix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 TLV2548 12 BIT, 8 Channel, Serial A/D converter 1.2.3

9、 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance wit

10、h MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style R GDIP1-T20 or CDIP2-T20 20 Dual-in-line 2 CQCC1-N20 20 Squar

11、e leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE

12、 A 5962-99570 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range, GND to VCC-0.3 V to 6.5 V Analog input voltage range . -0.3 V to VCC+ 0.3 V Reference input voltage VCC+ 0.3 V Digital input vo

13、ltage range . -0.3 V to VCC+ 0.3 V Maximum power dissipation, PD(TA 25C): Case R . 1894 mW 2/ Case 2 . 1375 mW 2/ Operating junction temperature range, TJ. -55C to 150C Storage temperature range . -65C to 150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds . 260C 1.4 Recommended operat

14、ing conditions. Supply voltage, VCC. 3.0 V min to 5.5 V max Positive external reference voltage input, VREFP2 V min to VCCmax 3/ Negative external reference voltage input, VREFM0 V min to 2 V max 3/ Differential reference voltage input, VREFP- VREFM2 V min to VCCmax 3/ Analog input voltage 0 V min t

15、o VCCmax 3/ High level control input voltage, VIH2.1 V min Low level control input voltage, VIL0.6 V max Setup time, CS falling edge before SCLK rising edge (FS = 1) or before SCLK falling edge (when FS is active), tsu(CS-SCLK)VCC= 4.5 V 20 ns min VCC= 3.0 V 30 ns min Hold time, CS rising edge after

16、 SCLK rising edge (FS = 1) or after SCLK falling edge (when FS is active), th(SCLK-CS)VCC= 4.5 V 10 ns min VCC= 3.0 V 15 ns min Delay time, delay from CS falling edge to FS rising edge, td(CSL-FSH). 0.5 SCLK min Delay time, delay time from 16thSCLK falling edge to CS rising edge (FS = 1), td(SCLK16L

17、-CSH)0.5 SCLK min Setup time, FS rising edge before SCLK falling edge, tsu(FSH-SCLKL). 20 ns min Hold time, FS hold high after SCLK falling edge, th(FSH-SCLKL)30 ns min to 37 ns max Pulse width, CS high time, twH(CS)100 ns min SCLK cycle time, VCC= 3.0 V to 3.6 V, tc(SCLK)67 ns min SCLK cycle time,

18、VCC= 4.5 V to 5.5 V, tc(SCLK)50 ns min Pulse width, SCLK low time, twL(SCLK)VCC= 4.5 V 22 ns min VCC= 3.0 V 27 ns min Pulse width, SCLK high time, twH(SCLK)VCC= 4.5 V 22 ns min VCC= 3.0 V 27 ns min Setup time, SDI valid before falling edge of SCLK (FS is active) or the rising edge of SCLK (FS = 1),

19、tsu(DI-SCLK)25 ns min Hold time, SDI hold valid after falling edge of SCLK (FS is active) or the rising edge of SCLK (FS = 1), th(DI-SCLK). 5 ns min Delay time, delay from CS falling edge to SDO valid, td(CSL-DOV). 25 ns max Delay time, delay from FS falling edge to SDO valid, td(FSL-DOV)25 ns max D

20、elay time, delay from SCLK falling edge (FS is active) or SCLK rising edge (FS = 1) to SDO valid, td(SCLK-DOV)VCC= 5.5 V, SDO = 60 pF . 0.5 times SCLK + 24 ns max VCC= 3.3 V, SDO = 60 pF . 0.5 times SCLK + 33 ns max 1/ Stresses above the absolute maximum rating may cause permanent damage to the devi

21、ce. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Case R, derate at 15.2 mW/C for TA 25C. Case 2, derate at 11.0 mW/C for TA 25C. 3/ When binary output format is used, analog input voltages greater than that applied to REFP convert as all ones (111111111

22、111), while input voltages less than that applied to REFM convert as all zeros (000000000000). The device is functional with reference down to 2 V (VREFP VREFM 1); however, the electrical specifications are no longer applicable. Provided by IHSNot for ResaleNo reproduction or networking permitted wi

23、thout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99570 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions Continued. Delay time, delay from 16thSCLK falling edge to INT falling edge (FS = 1)

24、 or from the 17thrising edge SCLK to INT falling edge (when FS active), td(SCLK-INTL)Min t(conv)Delay time, delay from CS falling edge to INT rising edge, td(CSL-INTH). 50 ns max Delay time, delay from CS rising edge to CSTART falling edge, td(CSH-CSTARTL)100 ns min Delay time, delay from CSTART ris

25、ing edge to EOC falling edge, td(CSTARTH-EOCL). 50 ns max Pulse width, CSTART low time, twL(CSTART)Min t(sample)Delay time, delay from CSTART rising edge to CSTART falling edge, td(CSTARTH-CSTARTL)t(conv)max Ambient operating temperature range, TA-55C TA 125C 2. APPLICABLE DOCUMENTS 2.1 Government s

26、pecification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and S

27、tandards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard

28、Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document

29、 Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99570 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEE

30、T 5 DSCC FORM 2234 APR 97 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has bee

31、n obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect t

32、he form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physica

33、l dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as

34、specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as

35、specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marke

36、d with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA pr

37、oduct using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device cl

38、asses Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufac

39、turer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to

40、DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of co

41、nformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notificati

42、on to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to re

43、view the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 81

44、(see MIL-PRF-38535, appendix A).Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99570 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrica

45、l performance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max High level output voltage VOHVCC= 5.5 V, IOH= -0.2 mA at 30 pF load 1,2,3 01 2.4 V VCC= 3.0 V, IOH= -20 A at 30 pF load 1,2,3 VCC 0.2 Low level output v

46、oltage VOLVCC= 5.5 V, IOL= 0.8 mA at 30 pF load 1,2,3 01 0.4 V VCC= 3.0 V, IOL= 20 A at 30 pF load 1,2,3 0.1 Off state output current (high impedance state) IOZVOUT= VCC, CS = VCC1,2,3 01 2.5 A VOUT= 0 V, CS = VCC1,2,3 -2.5 High level input current IIHVIN= VCC1,2,3 01 2.5 A Low level input current I

47、ILVIN= 0 V 1,2,3 01 2.5 A Operating supply current, normal sampling (short) ICCCS at 0 V, External reference, VCC= 4.5 V to 5.5 V 1,2,3 01 2.0 mA CS at 0 V, External reference, VCC= 3.0 V to 3.3 V 1,2,3 1.0 mA CS at 0 V, Internal reference, VCC= 4.5 V to 5.5 V 1,2,3 2.4 mA CS at 0 V, Internal refere

48、nce, VCC= 3.0 V to 3.3 V 1,2,3 1.7 mA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99570 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Internal reference supply current CS at 0 V, VCC