DLA SMD-5962-96513 REV G-2012 MICROCIRCUIT DIGITAL ADVANCED CMOS RADIATION HARDENED QUAD 2-INPUT NAND GATE TTL COMPATIBLE INPUTS MONOLTHIC SILICON.pdf
《DLA SMD-5962-96513 REV G-2012 MICROCIRCUIT DIGITAL ADVANCED CMOS RADIATION HARDENED QUAD 2-INPUT NAND GATE TTL COMPATIBLE INPUTS MONOLTHIC SILICON.pdf》由会员分享,可在线阅读,更多相关《DLA SMD-5962-96513 REV G-2012 MICROCIRCUIT DIGITAL ADVANCED CMOS RADIATION HARDENED QUAD 2-INPUT NAND GATE TTL COMPATIBLE INPUTS MONOLTHIC SILICON.pdf(26页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R070-97. jak 96-11-25 Monica L. Poelking B Incorporate NOR and update boilerplate to latest MIL-PRF-38535 requirements. CFS 01-06-11 Thomas M. Hess C Add appendix A to document. Update figure 4. Update boilerpl
2、ate to MIL-PRF-38535 and radiation hardness assurance boilerplate paragraphs. LTG 07-08-28 Thomas M. Hess D Correct circuit function on sheets 2 and 17. - LTG 09-02-25 Charles F. Saffle E Add device types 02 and 03. Update radiation hardness assurance paragraphs. Add table IB. - jak 10-11-16 Muhamma
3、d A. Akbar F To change RHA level H to G for device type 01. Update radiation features in section 1.5 and table IB. Update boilerplate paragraphs as required by the MIL-PRF-38535. - MAA 11-03-07 David J. Corbett G Add footnote 5 to figure 4. Add equivalent test circuit to figure 4. - jak 12-07-09 Tho
4、mas M. Hess REV SHEET REV G G G G G G G G G G SHEET 15 16 17 18 19 20 21 22 23 24 REV STATUS REV G G G G G G G G G G G G G G OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Thomas M. Hess DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Thomas M. Hess COLUMBUS, OH
5、IO 43218-3990 http:/www.dscc.dla.mil/ THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, ADVANCED CMOS, RADIATION HARDENED, QUAD 2-INPUT NAND GATE, TTL COMPATIBLE INPUTS, MONOLTHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPRO
6、VAL DATE 95-11-30 AMSC N/A REVISION LEVEL G SIZE A CAGE CODE 67268 5962-96513 SHEET 1 OF 24 DSCC FORM 2233 APR 97 5962-E392-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96513 DLA LAND AND MARITIME COLUM
7、BUS, OHIO 43218-3990 REVISION LEVEL G SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available
8、and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 G 96513 01 V X C Federal stock class designator RHA designator (see 1.2.1) Device type
9、 (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA mark
10、ed devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54ACTS00 Rad
11、iation hardened, quad 2-input NAND gate, TTL compatible inputs 02 54ACTS00E Enhanced, radiation hardened, quad 2-input NAND gate, TTL compatible inputs 03 54ACTS00E Enhanced, radiation hardened, quad 2-input NAND gate, TTL compatible inputs 1.2.3 Device class designator. The device class designator
12、is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and q
13、ualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style C GDIP1-T14 or CDIP2-T14 14 Dual-in-line X CDFP3-F14 14 Flat pack 1.2.5 Lead finish. The lead finish is as specifie
14、d in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96513 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LE
15、VEL G SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VDD) -0.3 V dc to +7.0 V dc DC input voltage range (VIN) -0.3 V dc to VDD+ 0.3 V dc DC output voltage range (VOUT) . -0.3 V dc to VDD+ 0.3 V dc DC input current (IIN) 10 mA Latch-up immunity current (ILU
16、) 150 mA Storage temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 5 seconds) +300C Thermal resistance, junction-to-case (JC): Case outline C and X, device type 01 See MIL-STD-1835 Case outline X, device types 02 and 03 . 15.5C/W Junction temperature (TJ) +175C Maximum package po
17、wer dissipation (PD): Device type 01 . 1.0 W Device types 02 and 03 . 3.2 W 4/ 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VDD): Device type 01 . +4.5 V dc to +5.5 V dc Device types 02 and 03 . +3.0 V dc to +5.5 V dc Input voltage range (VIN) +0.0 V dc to VDDOutput voltage rang
18、e (VOUT) . +0.0 V dc to VDDMaximum low level input voltage (VIL) 0.8 VDDMaximum Minimum high level input voltage (VIH) . 0.5 VDDMinimum Case operating temperature range (TC) . -55C to +125C Maximum input rise or fall time at VDD= 4.5 V (tr, tf) 1 ns/V 5/ 1.5 Radiation features. 6/ Maximum total dose
19、 available: Device type 01 (dose rate = 50 300 rads (Si)/s) 5 x 105rads (Si) 7/ Device type 02 (effective dose rate = 1 rad (Si)/s) . 1 x 106rads (Si) 8/ Device type 03 (dose rate = 50 300 rads (Si)/s) 5 x 105rads (Si) 7/ Single event phenomenon (SEP) : Device type 01: No SEU occurs at effective LET
20、 (see 4.4.4.4) . 80 MeV-cm2/mg 9/ No SEL occurs at effective LET (see 4.4.4.4) 120 MeV-cm2/mg 9/ Device types 02 and 03: No SEU occurs at effective LET (see 4.4.4.4) . 108 MeV-cm2/mg 9/ No SEL occurs at effective LET (see 4.4.4.4) 120 MeV-cm2/mg 9/ Dose rate upset (20 ns pulse) 1 x 109rads (Si)/s 9/
21、 10/ Dose rate latch-up . None 9/ Dose rate survivability . 1 x 1012 rads (Si)/s 9/ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all volt
22、ages are referenced to VSS.3/ The limits for the parameters specified herein shall apply over the full specified VDDrange and case temperature range of -55C to +125C unless otherwise specified. 4/ Per MIL-STD-883 method 1012.1 section 3.4.1, PD(Package) = (TJ (max) - TC(max). JC5/ Derate system prop
23、agation delays by difference in rise time to switch point for tror tf 1 ns/V. 6/ Radiation testing is performed on the standard evaluation circuit (SEC). 7/ Device types 01 and 03 are tested in accordance with MIL-STD-1019, condition A. 8/ Device type 02 is irradiated at dose rate = 50 - 300 rads (S
24、i)/s in accordance with MIL-STD-883, method 1019, condition A, and is guaranteed to a maximum total dose specified. The effective dose rate after extended room temperature anneal = 1 rad (Si)/s per MIL-STD-883, method 1019, condition A, section 3.11.2. The total dose specification for these devices
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