DLA SMD-5962-95627 REV E-2011 MICROCIRCUIT MEMORY DIGITAL 1024 X 18 CLOCKED FIFO MONOLITHIC SILICON.pdf

《DLA SMD-5962-95627 REV E-2011 MICROCIRCUIT MEMORY DIGITAL 1024 X 18 CLOCKED FIFO MONOLITHIC SILICON.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-95627 REV E-2011 MICROCIRCUIT MEMORY DIGITAL 1024 X 18 CLOCKED FIFO MONOLITHIC SILICON.pdf（23页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated test load circuit and table. 96-02-14 M. A. Frye B Added case outline “Y“. Updated boilerplate. 97-06-23 Raymond Monnin C Changes in accordance with NOR 5962-R007-98 97-11-18 Raymond Monnin D Updated boilerplate paragraphs. ksr 05-04-04 R

2、aymond Monnin E Updated boilerplate for 5 year review. lhl 11-04-05 Charles F. Saffle REV SHEET REV E E E E E E E E SHEET 15 16 17 18 19 20 21 22 REV STATUS REV E E E E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DLA LAND AND MARITIME COLUM

3、BUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL, 1024 X 18 CLOCKED FIFO, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWI

4、NG APPROVAL DATE 95-11-09 AMSC N/A REVISION LEVEL E SIZE A CAGE CODE 67268 5962-95627 SHEET 1 OF 22 DSCC FORM 2233 APR 97 5962-E297-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95627 DLA LAND AND MARITI

5、ME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents three product assurance class levels consisting of space application (device class V), high reliability (device classes M and Q), and nontraditional performance environment (device

6、class N). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. For device class N, the user is cautioned to assure that the device is approp

7、riate for the application environment. 1.2 PIN. The PIN is as shown in the following example: 5962 - 95627 01 N X D Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing numbe

8、r 1.2.1 RHA designator. Device classes N, Q, and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA desi

9、gnator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type identify the circuit function as follows: Device Type Generic Number Circuit Function 01 ACT7881 1024 X 18 clocked FIFO 1.2.3 Device class designator. The device class designator is a single letter identifying the p

10、roduct assurance level as follows: Device Class Device Requirements Documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN Class Level B microcircuits in accordance with MIL-PRF-38535, Appendix A. N Certification and qualification to MIL-PRF-38535 with a non

11、traditional performance environment (encapsulated in plastic). Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835, JEDEC Publication 95, and as follows: Outline Letter Descriptive Designator Terminals Package Style Doc

12、ument X MS-026 BDD 80 Plastic small outline package JEP 95 Y See figure 1 68 Ceramic quad flat package 1.2.5 Lead Finish. The lead finish is as specified in MIL-PRF-38535 for device Classes N, Q, V or MIL-PRF-38535, appendix A for device class M. 1.2.5.1 Lead finish D. Lead finish D shall be designa

13、ted by a single letter as follows: Finish letter Process D Palladium Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95627 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 3 DSCC FORM 22

14、34 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage (VIN) 7.0 V dc Voltage applied to adisabled 3-stateoutput . 5.5 V dc Operating free-air temperature range (TA) . -55C to +125C Storage temperature range (TSTG) . -65C to +150C 1.4 Reco

15、mmended operating conditions. 2/ 3/ Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Maximum low level input voltage (VIL) +0.8 V Minimum high level input voltage (VIH) . +2.0 V Maximum high level output current (IOH) -8.0 mA Maximum low level output current (IOL) +16.0 mA Case operating temperatur

16、e range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in

17、the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEP

18、ARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building

19、4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation. ELECTRONICS INDUSTRIES ALLIANCE (EIA) JEDEC Standard

20、JEP 95 - Registered and Standard Outlines for Semiconductor Devices JEDEC Standard EIA/JESD78 - IC Latch-Up Test. (Copies of this document are available online at www.jedec.org/ or from the JEDEC Office, 3103 North 10thStreet, Suite 240-S, Arlington, VA 22201-2107). 2.3 Order of precedence. In the e

21、vent of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 1/ Stresses above the absolute maximum rating m

22、ay cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise noted, all voltages are referenced to GND. 3/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case tem

23、perature range of -55C to +125C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95627 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item r

24、equirements. The individual item requirements for device classes N, Q, and V shall be in accordance withMIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as descri

25、bed herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

26、in MIL-PRF-38535 and herein for device classes N, Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure

27、 2. 3.2.3 Block diagram(s). The block diagram(s) shall be as specified on figure 3. 3.2.4 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwi

28、se specified herein, the electrical performance characteristics and post-irradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in tab

29、le IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the

30、 manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes N, Q, and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535,

31、appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes N, Q, and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device class

32、es N, Q, and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved sou

33、rce of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes N, Q, and V, the requirements of MIL-PRF-38535

34、 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes N, Q, and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of

35、microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DLA Land and Maritime-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification

36、 and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritimes agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of th

37、e reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICR

38、OCIRCUIT DRAWING SIZE A 5962-95627 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device types Group A subgroups2

39、/ Limits 3/ Unit Min Max High level output voltage VOHFor all inputs affecting output under test, VIN= 2.0 V or 0.8 V,IOH= -8.0 mA, VCC= 4.5 V 01 1, 2, 3 2.4 V Low level output voltage VOLFor all inputs affecting output under test, VIN= 2.0 V or 0.8 V,IOL= 16 mA, VCC= 4.5 V 01 1, 2, 3 0.5 V Input cu

40、rrent II 4/ For input under test, VI= VCCor GND, VCC= 5.5 V 01 1, 2, 3 +5 A Three-state output leakage current high IOZH5/ For control input affecting output under test, VIN= 2.0 V or 0.8 V,VOUT= VCC, VCC= 5.5 V 01 1, 2, 3 5 A Three-state output leakage current low IOZL5/ For control input affecting

41、 output under test, VIN= 2.0 V or 0.8 V,VOUT= GND, VCC= 5.5 V 01 1, 2, 3 -5 A Quiescent supply current ICC 6/ For input under test, VIN= VCC-0.2V or 0 VCC= 5.5 V 01 1, 2, 3 400 A One input at 3.4 V. For all other inputs VIN= VCCor GND. VCC= 5.5 V 1.2 mA Input capacitance CINTA= +25C, VBIAS= 0 V VCC=

42、 5.0 V, See 4.4.1e f = 1 MHz VI= 0 01 4 4 pF Output capacitance COVO= 0 4 8 Functional tests 7/ VIH= 2.0 V, VIL= 0.8 V, verify output VO, VCC= 4.5 V and 5.5 V, 4.4.1c 01 7, 8A, 8B L H Clock frequency CLKA or CLKB fclockCL= 20 pF minimum, VCC= 4.5 V and 5.5V, see figure 4 as applicable 01 9, 10, 11 5

43、0 MHz Pulse duration, WRTCLK high tw101 9, 10, 11 7 ns Pulse duration, WRTCLK low tw201 9, 10, 11 7.5 Pulse duration, RDCLK high tw301 9, 10, 11 7 Pulse duration, RDCLK low tw401 9, 10, 11 7 Pulse duration, DAF high tw501 9, 10, 11 7 Setup time, D0-D17 before WRTCLK tsu101 9, 10, 11 5 Setup time, WR

44、TEN1, WRTEN2 high before WRTCLK tsu201 9, 10, 11 5 Setup time, OE, RDEN1, RDEN2 high before RDCLK tsu301 9, 10, 11 5 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95627 DLA LA

45、ND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Test conditions 1/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device types Group A subgroups2/ Limits 3/ Unit Min Max Setu

46、p time, Define AF/AE: D0-D8 before DAF tsu4CL= 20 pF minimum, VCC= 4.5 V and 5.5 V, see figure 4 as applicable 01 9, 10, 11 5 ns Setup time, Define AF/AE: DAF before RESET tsu501 9, 10, 11 6 Setup time, Define AF/AE (default): DAF high before RESET tsu601 9, 10, 11 5 Hold time, D0-D17 after WRTCLK t

47、h101 9, 10, 11 0 Hold time, WRTEN1, WRTEN2 high after WRTCLK th201 9, 10, 11 0 Hold time, OE, RDEN1, RDEN2 high after RDCLK th3 01 9, 10, 11 0.5 Hold time, Define AF/AE: D0-D8 after DAF th4 01 9, 10, 11 1 Hold time, Define AF/AE: DAF low after RESET th5 01 9, 10, 11 0 Hold time, Define AF/AE (defaul

48、t): DAF high after RESET th6 01 9, 10, 11 0 Maximum frequency WRTCLK or RDCLK fmax01 9, 10, 11 50 MHz Propagation delay time, RDCLK to any Q tpd101 9, 10, 11 3 13 ns Propagation delay time, WRTCLK to IR tpd201 9, 10, 11 2 9.5 Propagation delay time, RDCLK to OR tpd301 9, 10, 11 2 9.5 Propagation delay time, WRTCLK or RDCLK to AF/AE tpd401 9, 10, 11 6 19 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95