DLA SMD-5962-95600 REV K-2009 MICROCIRCUITS MEMORY DIGITAL CMOS 512K X 8 STATIC RANDOM ACCESS MEMORY (SRAM) MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Change minimum limit of dimension Q for case outline T. Changes in accordance with NOR 5962-R145-97. 96-11-27 Raymond Monnin B Add note 4/ to tWLQZ, tCDR, and tRin table I. Add note 5/ to tELQX, tWHQX, tOLQX, and tOHQZin table I. Add case outline 8. Change
2、dimensions b, c, L, and Q for case outline T. Add CAGE 01295 as source of supply for case outlines T and 8. Update boilerplate. Editorial changes throughout. 97-04-17 Raymond Monnin C Change minimum dimensions A, b, and E for case outline U. Add CAGE 65786 as a source of supply . Editorial changes t
3、hroughout. - ksr 97-10-24 Raymond Monnin D Change case outline 9 dimension A from .114 inches to .130 inches. - glg 00-03-01 Raymond Monnin E Added low-power devices 09 - 14 to drawing. Removed CAGE 0EU86 for devices 05 - 08. - glg 00-11-22 Raymond Monnin F Changed minimum dimension b for package “U
4、“ from 0.015 inches to 0.012 inches. - glg 00-12-13 Raymond Monnin G Changed minimum dimension b for package “M“ from 0.019 inches to 0.012 inches. Updated boilerplate paragraphs. ksr 02-02-12 Raymond Monnin H Table I; Changed the IOLfrom 8 mA to 6 mA VOLtest. Added device types 15 and 16. Editorial
5、 changes throughout. -sld 04-05-25 Raymond Monnin J Add case outline 7. Add CAGE 0EU86 as source of supply for case outline 7. Editorial changes throughout. tcr 08-08-18 Robert M. Heber K Add device 17 and add case outline 6. Add CAGE 6S055 as source of supply for case outline 6. Some editorial chan
6、ges. ksr 09-01-22 Robert M. Heber REV SHEET REV K K K K K K K K K K K K K K K K K K SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 REV STATUS REV K K K K K K K K K K K K K K OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Jeff Bowling STANDARD MICROCIRCUIT DRAWING
7、CHECKED BY Jeff Bowling DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil/ THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY Michael. A. Frye AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 96-03-05 MICROCIRCUITS, MEMORY, DIGITAL, CMOS, 51
8、2K X 8 STATIC RANDOM ACCESS MEMORY (SRAM), MONOLITHIC SILICON AMSC N/A REVISION LEVEL K SIZE A CAGE CODE 67268 5962-95600 SHEET 1 OF 32 DSCC FORM 2233 APR 97 5962-E130-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-95600 STANDARD MICR
9、OCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL K SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A cho
10、ice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 5962 - 95600 01 M X A Federal stock class designator RHA designator (see 1.2.1) Devicetype (
11、see 1.2.2)Deviceclass designatorCaseoutline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked dev
12、ices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device types identify the circuit function as follows: Device type Generic number 1/ Circuit function Data retention Acces
13、s time 01 512K X 8 CMOS SRAM No 45 ns 02 512K X 8 CMOS SRAM No 35 ns 03 512K X 8 CMOS SRAM No 25 ns 04 512K X 8 CMOS SRAM No 20 ns 05 512K X 8 CMOS SRAM Yes 45 ns 06 512K X 8 CMOS SRAM Yes 35 ns 07 512K X 8 CMOS SRAM Yes 25 ns 08 512K X 8 CMOS SRAM Yes 20 ns 09 512K X 8 CMOS Low Power SRAM Yes 45 ns
14、 10 512K X 8 CMOS Low Power SRAM Yes 35 ns 11 512K X 8 CMOS Low Power SRAM Yes 25 ns 12 512K X 8 CMOS Low Power SRAM Yes 20 ns 13 512K X 8 CMOS Low Power SRAM Yes 15 ns 14 512K X 8 CMOS SRAM No 15 ns 15 512K X 8 CMOS SRAM Yes 12 ns 16 512K X 8 CMOS SRAM No 12 ns 17 512K X 8 CMOS SRAM Yes 12 ns 1.2.3
15、 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance wit
16、h MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and will also be listed in MIL-HDBK-103 and QML-38535, as applicable (see 6.6.1 and 6.6.2 herein
17、). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-95600 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL K SHEET 3 DSCC FORM 2234 APR 97 1.2.4 Case outlines. The case outlines are as d
18、esignated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GDIP1-T32 or CDIP2-T32 32 Dual-in-line Y See figure 1 32 TSOP package Z See figure 1 32 Leadless chip carrier U See figure 1 32 SOJ package T See figure 1 36 Flat pack M See figure 1 36 SOJ pack
19、age N See figure 1 36 Leadless chip carrier 9 See figure 1 32 Flat pack 8 See figure 1 36 SOJ package 7 See figure 1 36 SOJ package 6 See figure 1 44 TSOP package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device cl
20、ass M. 1.3 Absolute maximum ratings. 2/ Voltage on any input relative to VSS-0.5 V dc to +7.0 V dc For device 17 only -0.5 V dc to +6.0 V dc Storage temperature range -65C to +150C Maximum power dissipation (PD) 2.0 W Lead temperature (soldering, 10 seconds). +260C Thermal resistance, junction-to-ca
21、se (JC): Case X See MIL-STD-1835 Case Y 6C/W Cases U, M, 8 and 7. 11C/W Case T 10C/W Cases Z and N 20C/W Case 9 22C/W Case 6 7 C/W Junction temperature (TJ). +150C 2/ For - 17 +140C 2/ Output current. 40 mA 1.4 Recommended operating conditions. Supply voltage range (VCC). 4.5 V dc to 5.5 V dc Supply
22、 voltage (VSS) . 0 V Input high voltage range (VIH) Devices 01 - 08. 2.2 V dc to +6.0 V dc Input high voltage range (VIH) Devices 09 - 13. 2.2 V dc to VCC+ 0.3 V dc Input high voltage range (VIH) Device 17 2.0 V dc to VCC+ 0.5 V dc Input low voltage range (VIL). -0.5 V dc to +0.8 V dc 3/ Case operat
23、ing temperature range (TC) . -55C to +125C _ 2/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 3/ VILminimum = -3.0 V dc for pulse width less than 20 ns. Provided by IHSNot for ResaleN
24、o reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-95600 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL K SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks.
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