DLA SMD-5962-92344 REV A-2013 MICROCIRCUIT MEMORY DIGITAL BICMOS 8K X 8 RESETTABLE SRAM MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated boilerplate to current requirements. lhl 13-02-06 Charles F. Saffle REV SHEET REV A A A A A A A SHEET 15 16 17 18 19 20 21 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Je

2、ff Bowling DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Jeff Bowling APPROVED BY Michael A. Frye MICROCIRCUIT, MEMORY, DIGITAL,

3、 BICMOS 8K X 8 RESETTABLE SRAM, MONOLITHIC SILICON DRAWING APPROVAL DATE 93-12-16 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-92344 SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E137-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MI

4、CROCIRCUIT DRAWING SIZE A 5962-92344 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents three product assurance class levels consisting of space application (device class V), high reliability (device class M and Q

5、). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 92344 01 M X A Federal

6、stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device class Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked w

7、ith the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows:

8、Device type Generic number Circuit function Access time 01 71B74 8K X 8 SRAM, resettable 20 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification

9、to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 as follows: Outline letter Descriptive

10、designator Terminals Package style X CQCC1-N32 32 Rectangular leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted wit

11、hout license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92344 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +7.0 V Voltage on any pin with respect to GND (VTERM) rang

12、e . -0.5 V dc to +7.0 V 2/ Storage temperature range -65C to +150C Thermal resistance, junction-to-case (JC) 20C/W Junction temperature. 150C Power dissipation. 1.0 W DC output current. 50 mA Terminal soldering, temperature range (10 seconds). 275C 1.4 Recommended operating conditions. Supply voltag

13、e range 4.5 V dc to 5.5 V dc High level input voltage range (VIH) 2.2 V dc to 6.0 V dc 2/ 3/ Low level input voltage range (VIL) -0.5 V dc to +0.8 V dc 4/ Case operating temperature range (TC). 55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following

14、 specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, Gene

15、ral Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit D

16、rawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to th

17、e extent specified herein. Unless otherwise specified, the issues of the documents which are DoD adopted are those listed in the issue of the DoDISS cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DoDISS are the issues of the documents cited in the so

18、licitation. JEDEC JEDEC INTERNATIONAL JESD 78 - IC Latch-Up Test. (Copies of this document are available online at www.jedec.org/ or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201) _ 1/ Stresses above the absolute maximum rating may cause perm

19、anent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ VTERM must not exceed VCC + 0.5 V. 3/ All inputs except reset. 4/ VIL (min) = -3.0 V for pulse width less than 5 ns. Provided by IHSNot for ResaleNo reproduction or networking perm

20、itted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92344 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the

21、text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-3

22、8535 and as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appen

23、dix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class

24、M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table(s) shall be as specified on figure 2. 3.2.4 Functional algorithms. Various functional alg

25、orithms used to test this device are contained in appendix A (herein). If the test patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed. For device classes Q and V, alternate test patterns shall be under the control

26、 of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. 3.2.5 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only.

27、 Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor testing shall not be decreased unless approved by the pr

28、eparing activity for class M. The TRB will ascertain the requirements as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical perfor

29、mance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgr

30、oup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking

31、 the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark

32、. The certification mark for device classes Q, and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be r

33、equired from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The

34、certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL

35、-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot fo

36、r ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92344 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 3.8 Notification of change for device class M. For device class M, notification

37、to DLA Land and Maritime-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DLA Land and Maritime, DLA Land and Maritimes agent, and the acquirin

38、g activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall b

39、e in microcircuit group number 042 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92344 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 223

40、4 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Limits Unit unless otherwise specified Min Max Input leakage current ILI VCC = maximum VIN = GND to VCC 1, 2, 3 10.0 A Output leakage current ILO VCC = maximum VOUT = GND

41、to VCC CS = VIH 1, 2, 3 10.0 A Input LOW level voltage VIL 1, 2, 3 -0.5 0.8 V Input HIGH level voltage (except for RESET input) VIH All inputs except RESET input 1, 2, 3 2.2 VCC +0.5 V Input HIGH level voltage (for RESET input) VIHR For RESET input only 1, 2, 3 2.5 VCC +0.5 V Output LOW voltage (MAT

42、CH output) VOL1 MATCH output IOL = 18 mA VCC = minimum 1, 2, 3 0.4 V Output LOW voltage (MATCH output) VOL2 MATCH output IOL = 22 mA VCC = minimum 1, 2, 3 0.5 V Output HIGH voltage (except MATCH output) VOL3 IOL = 10 mA VCC = minimum Except MATCH output 1, 2, 3 0.5 V Output LOW voltage (except MATCH

43、 output) VOL4 IOL = 8 mA VCC = minimum Except MATCH output 1, 2, 3 0.4 V Output HIGH voltage (except MATCH output) VOH IOH = -4 mA VCC = minimum 1, 2, 3 2.4 V Dynamic operating current ICC1 VCC = maximum f = fMAX 1/, IOUT = 0 mA, CS = VIL, WE = VIL 1, 2, 3 190 mA Dynamic operating current ICC2 VCC =

44、 maximum f = fMAX 1/, IOUT = 0 mA, CS = VIL, WE = VIL 1, 2, 3 160 mA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92344 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISI

45、ON LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Limits Unit unless otherwise specified Min Max Input capacitance CIN VIN = 0V, f = 1 MHz, See 4.4.1e 2/ 4 7 pF Output capacitan

46、ce COUT VOUT = 0V, f = 1 MHz, See 4.4.1e 2/ 4 8 pF Functional tests See 4.4.1c 7, 8A, 8B READ CYCLE TIMING Read cycle time tAVAV 3/ 9, 10, 11 20 ns Address access time tAVQV 9, 10, 11 20 ns Chip Select access time tSLQV 9, 10, 11 10 ns Chip Select to output in LOW Z 2/ tSLQX 9, 10, 11 3 ns Output en

47、able to output valid tOLQV 9, 10, 11 9 ns Output enable to output in LOW Z 2/ tOLQX 9, 10, 11 2 ns Chip Select to output in HIGH Z 2/ tSHQZ 9, 10, 11 8 ns Output disable to output in HIGH Z 2/ tOHQZ 9, 10, 11 8 ns Output hold from address change tAVQX 9, 10, 11 3 ns WRITE CYCLE TIMING WRITE cycle ti

48、me tAVAV 3/ 9, 10, 11 20 ns Chip Select to end of write tSLSH 9, 10, 11 15 ns Address valid to end of write tAVSH 9, 10, 11 15 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92344 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LE