DLA SMD-5962-92282-1996 MICROCIRCUIT DIGITAL FAST CMOS 20-BIT NONINVERTING TRANSPARENT LATCH WITH CURRENT LIMITING RESISTORS AND THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS AND LIMIT.pdf

《DLA SMD-5962-92282-1996 MICROCIRCUIT DIGITAL FAST CMOS 20-BIT NONINVERTING TRANSPARENT LATCH WITH CURRENT LIMITING RESISTORS AND THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS AND LIMIT.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-92282-1996 MICROCIRCUIT DIGITAL FAST CMOS 20-BIT NONINVERTING TRANSPARENT LATCH WITH CURRENT LIMITING RESISTORS AND THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS AND LIMIT.pdf（20页珍藏版）》请在麦多课文档分享上搜索。

1、LTR DESCRIPTION DATE (YR-MO-DA) SUD-59b2-92282 9999996 008BbL 720 = APPROVED I REV III SIZE A SHEET SHEET CAGE CODE 5962-92282 67268 REV STATUS OF SHEETS PMIC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A REV

2、 SHEET 1 2 3 4 5 6 7 8 9 1011 121314 PREPARED BY Thanh V. Nguyen DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 bnLbnLu PI Thanh V. Nguyen APPROVED BY Monica L. Poelking DRAWING APPROVAL DATE 96-06-1 2 REVISION LEVEL MICROCIRCUIT, DIGITAL, FAST CMOS, 20-BIT NONINVERTING TRANSPARENT LATCH WITH

3、OUPTPUTS, TTL COMPATIBLE INPUTS AND LIMITED OUTPUT VOLTAGE SWING, MONOLITHIC SILICON CURRENT LIMITING RESISTORS AND THREE-STATE SHEET 1 OF 19 DESC FORM 193 JUL 94 5962-E455-96 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. Provided by IHSNot for ResaleNo reproducti

4、on or networking permitted without license from IHS-,-,-1. SCOPE 1.1 m. This drawing docunents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). and are reflected in the Part or Identifying Nunber (PIN). hen available,

5、a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. A choice of case outlines and lead finishes are available 1.2 m. The PIN is as shown in the following example: 97782 1 1 Federal RHA Devi ce Device Case Lead stock class designator type class outline finish designator (s

6、ee 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) Il LA (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. specified RHA levels and are marked with the app

7、ropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A A dash (-1 indicates a non-RHA device. 1.2.2 Device tvwtsl . The device typeCs) identify the circuit function as follows: Devi ce te Generic nunber Circuit function o1 54FCT162841AT 20-bit noninverting tran

8、sparent latch with current limiting resistors and three-state outputs, TTL compatible inputs and limited output voltage swing 02 54FCT162841BT 20-bit noninverting transparent latch with current Limiting resistors and three-state outputs, TTL canpatible inputs and limited output voltage swing 20-bit

9、noninverting transparent latch with current limiting resistors and three-state outputs, TTL compatible inputs and limited output voltage swing 03 54FCT162841CT 1.2.3 pevice class desianator. The device class designator is a single letter identifying the product assurance level as follows: pevice cla

10、ss Device reauirements documentation STAN DARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 M SIZE A 5962-92282 REVISION LEVEL SHEET 2 Vendor self-certification to the requirements for MIL-STO-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-

11、38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outlineCs1. The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline lette r pescrimive desimator Temi na Is Package stv le X GDFPl -F56 56 Flat pack DESC FORM 193A JUL 94 Provided by IHSNot for

12、 ResaleNo reproduction or networking permitted without license from IHS-,-,- SID-5762-92282 m 9999996 0088621 389 m SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 r REVISION LEVEL 1.3 Absolute maximum ratinqs. r/ 2/ 5/ Supply voltage range (V ) DC input voltag

13、e range FY,) . DC output voltage range (V ) DC input clamp current (I TCVIN = -0.5 V ) . DC output clamp current (1 ) (VWT = -0.5 V and +7.0 V) . DC output source current (YK,) (per output) . DC V current (Icc) . Grou2 current (IGND) Storage temperature range (T . Case temperature under bias ?!BiAs)

14、 . Lead temperature (soldering, seconds) . Thermal resistance, junction-to-case (eJc) . Maximum power dissipation (P,) DC output sink current (IoL? (per output) Junction temperature (TJ) 1.4 Recomnended owratins conditions. a 2/ Supply voltage range (Vcc) Maxim low levei input voltage (VIL) Minimum

15、high level input voltage (VI“) Case operating temperature range (TC) Maxim input rise or fall rate (At/Av): Maxim high level output current (IoH) . Maximum Low Level output current (IoL) Input voltage range (VIN) Output voltage range (VWT) . (from VIN = 0.3 V to 2.7 V, 2.7 V to 0.3 V) 1.5 Disital Lo

16、sic test ins for device classes (3 and V. 5962-92282 SHEET 3 -0.5 V dc to +7.0 V dc -0.5 V dc to Vcc + 0.5 V dc -0.5 V dc to Vcc -20 mA t20 mA -30 mA +70 mA t480 m4 +I120 mA -65C to +150C -65C to +135“C and the preferred method and limits are guaranteed. shall be the measured values of these paramet

17、ers, for the in table I, herein. Classes Q and V shall use the preferred method. When the test is performed o/ ICCT is calculated as follows: ICCT = ICC + DHNTAICC + ICCD(fCp/Z + fiNi) where Icc = Quiescent supply current (any IccL or ICCH) DH = Duty cycle for TTL inputs at 3.4 V NT = Nunber of TTL

18、inputs at 3.4 V AIcc= Quiescent supply current delta, TTL inputs at 3.4 V I fEr=-Clock frequency for registered devices (fCp = O for nonregistered devices) fi = Input frequency Ni = Nunber of inputs at fi Dynamic power supply current caused by an input transition pair (HLH or LHL This test is requir

19、ed only for group A testing; see 4.4.1 herein. This test is for qualification only. Ground and V output and are used to measure the magnitude of ir%ced noise caused by other simultaneously switching outputs. The test is performed on a low noise bench test fixture. with 500n of load resistance and a

20、minimum of 50 pF of load capacitance (see figure 4). resistors shall be used. It is suggested, that whenever possible, this distance be kept to less than 0.25 inches. shall be placed in parallel from Vcc to ground. the device manufacturer. The Lou and high level ground and V a 1 GHz minimun bandwidt

21、h oscilloscope with a 50n input i duty cycle = 50 percent; fIN a 1 MHz. rf =-3 ns k1.0 ns. For input signal generators incapable of maintaining these values of tr and tf, the i 250 ps. 3.0 ns limit may be increased up to 10 ns, as needed, maintaining the 1.0 ns tolerance and guaranteeing the results

22、 at 3.0 ns 21.0 ns; skew between any two switching inputs signals (t,k): FIGURE 4. Ground bunce load circuit and waveforms. 5962-92282 REVISION LEVEL STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction

23、or networking permitted without license from IHS-,-,-3.0 v 1.5 v INPUT DATA 0.0 v INPUT 3.0 v LATCH ENABLE 1.5 v CONTROL INPUT 0.0 v 0.3 v STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 LATCH / 3.0 v SIZE A 5962-92282 REVISION LEVEL SHEET 14 ENABLE CONTROL 1.5 v +

24、 INPUT d 0.0 v OUTPUT 1.5 v OH L OL F OH OUTPUT I k 1.5 v Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-57b2-92282 b 0088633 OTO ltf . 2.7 v 3.0 V 7 - REVISION LEVEL DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 II 4 1.5 v SHEET 15 CONTR

25、OL INPUT OUTPUT OUTPUT INPUT OUTPU OUTPU I 0.0 “Oe3 t - PLZ - NVCC 1.5 v + 0.3 V VOL t r- PZH “OH VOH - 0.3 V 1.5 v N GND 3*0 1.5 v 0.0 v 2.7 V -0.3 v I OH 2 I/ L- VOL A FIGURE 5. Switchins waveforms and test circuit - Continued. STANDARD MICROCIRCUIT DRAWING 1 5962-92282 I I I DESC FORM 193A JUL 94

26、 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-92282 9 b 0088634 T37 SIZE A STAN DARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 . LL “TEST OTHER INPUTS TIED , I 5962-92282 REVISION LEVEL SHEET 16 DEVICE I I

27、“IN PULSE - ;iRL Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-92282 9999996 0088635 973 SIZE A STAN DARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL 4.4 Conformance inswction. Technology confor

28、mance inspection for classes P and V shall be in accordance with MIL- RF-38535 including groups A, B, C, D, and E inspections and as specified herein except uhere option Z of UL-PRF-38535 permits alternate in-line control testing. Quality conformance inspection for device class M shall be in accorda

29、nce with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4.1 GrouD A insDection. 5962-92282 SHEET 17 a. b. C. d. T

30、ests shall be as specified in table II herein. C a#ect capacitance. CIN and CaU shall be measured between the designated terminal and GND at a frequency of 1 MHz. For CI# and CWT, test a11 applicable pins on five devices with zero failures. :i: I Land OUT accordance with table I herein. Co tests. ad

31、 conditions specified herein. guaranteed, if not tested, to the limits and conditions specified in table I herein. The device manufacturer shall submit to DESC-EC the device functions listed in each functional group and the test results for each device tested. and COUT.sha1l be measured only for ini

32、tial qualification and after process or design changes which may a device manufacturer may qualify devices by functional groups. A specific functional group composed of function types, that by design, will yield the same capacitance values uhen tested in The device manufacturer shall set a functiona

33、l group limit for the CI and The device manufacturer may then test one device function from a functional group to the rimits All other device functions in that particular functional group shall be For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 h

34、erein. The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2 herein. For device classes Q and V, subgroups 7 and 8 s

35、hall include verifying the functionality of the device; these tests shall have been fault graded in accordance with MIL-STD-883, test method 5012 (see 1.5 herein). Ground and V initial qual%ication, after process or design changes which may affect the performance of the device, and any changes to th

36、e test fixture. V device. All other outputs guaranteed, if not tested, to the limits established for the Worst case outputs. the worst case package type supplied to this docunent. All other package types shall be guaranteed, if not tested, to the limits established for the worst case package. determ

37、ined by the manufacturer. The device manufacturer will submit to DESC-EC data that shall include all measured peak values for each device tested and detailed oscilloscope plots for each VoLp,.Vo , VOHp, and V HV from one sample part per function. The plot shall contain the waveforms of both a switck

38、ing output and tie output under test. Each device manufacturer shall test product on the fixtures they currently use. When a new fixture is used, the device manufacturer shall inform DESC-EC of this change and test the 5 devices on both the neu and old test fixtures. The device manufacturer shall th

39、en submit to DESC-EC data from testing on both fixtures that shall include all measured peak values for each device tested and detailed oscilloscope plots for each VOLPI VOLV. VOHP, and VoHv from one sample part per function. switching output and the output under test. For VOLPI VOLVI Vo p, and VOHV

40、, a device manufacturer may qualify devices by functional groups. A specific functional group slat1 be composed of function types, that by design, will yield the same test values when tested in accordance with table I herein. bounce tests are required for all device classes. These tests shall be per

41、formed only for VOLV. VOHp, and VoHv shall be measured for the worst case outputs of the The worst case outputs tested are to be determined by the manufacturer. Test 5 devices assembled in The package type to be tested shall be The plot shall contain the waveforms of both a The device manufacturer s

42、hall set a functional group limit for the tests. group shall be guaranteed, if not tested, to the limits and conditions specified in table I herein. device manufacturer shall submit to DESC-EC the device functions listed in each functional group and the test results, along with the oscilloscope plot

43、s, for each device tested. The device manufacturer may then test one device function from a functional specified herein. All other device functions in that particular functional The 4.4.2 GrOUD C insDection. The group C inspection end-point electrical parameters shall be as specified in table II her

44、ein. DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SUD-5962-92282 = 9999996 0088636 BOT W I TABLE II. Flectrical test reauirements. Test requirements Interim electrical parameters (see 4.2) Final electrical parameters (see 4.2

45、) Group A test Group C end-point electrical Group D end-point electrical Group E end-point electrical requirements (see 4.4) parameters (see 4.4) parameters (see 4.4) parameters (see 4.4) Subgroups Subgroups (in accordance with MIL-STD-883, method MIL-PRF-38535, table III) 5005, table I) (in accorda

46、nce with Devi ce Devi ce Device class M class Q class V 1 1 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 61 - 1, 2, 3, 4, 5, 61 7, 8, 9, IO, 11 7, 8, 9, IO, 11 7, 8, 9, IO, 11 1/ 1/ 2/ 1, 2, 3, 4, 5, 6, 1, 2, 3, 4. 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6 1, 2, 3, 4, 5. 6 1, 2, 3, 4, 5, 6 1, 2. 3 1, 2, 3 1, 2.

47、3 1. 4, 7, 9 1, 4, 7, 9 1, 4, 7, 9 7, 8, 9, IO, 11 7, 8, 9, IO, 11 7, 8, 9, IO, 11 7, 8, 9, IO, 11 STANDARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 SIZE A 5962-92282 REVISION LEVEL SHEET 18 Provided by IHSNot for ResaleNo reproduction or networking permitted without li

48、cense from IHS-,-,-SMD-5962-72282 m 9999996 0088637 746 4.5 Methods o f insoection. Methods of inspection shall be specified as follows: 4.5.1 :erminal. Voltaae and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND Currents given are conventional current

49、and positive when flowing into the referenced terminal. 5. PACKAGING 5.1 Packaaina reauirementg. :lasses Q and V or MIL-PRF-38535, appendix A for device class M. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Govermient microcircuit ippl icat i ons (origina 1 qui pme