DLA SMD-5962-89971-1992 MICROCIRCUIT DIGITAL HMOS REMOTE UNIVERSAL PERIPHERAL INTERFACE MONOLITHIC SILICON《硅单片 远程通用外围接口 高性能金属氧化物半导体数字微型电路》.pdf

《DLA SMD-5962-89971-1992 MICROCIRCUIT DIGITAL HMOS REMOTE UNIVERSAL PERIPHERAL INTERFACE MONOLITHIC SILICON《硅单片 远程通用外围接口 高性能金属氧化物半导体数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-89971-1992 MICROCIRCUIT DIGITAL HMOS REMOTE UNIVERSAL PERIPHERAL INTERFACE MONOLITHIC SILICON《硅单片 远程通用外围接口 高性能金属氧化物半导体数字微型电路》.pdf（28页珍藏版）》请在麦多课文档分享上搜索。

1、* SMD-5962-89771 59 9999996 001299 2 SPPLY 2Et4TER BAVION., OHIO 45444 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-I I I I I I I I I 1 STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 i I I I I I I I L, SIZE 5962

2、-89971 A REVISION LEVEL SHEET 11 LATOR TIMING PROGRAM MEMORY I OATA I/O HDLC/SDLC SERIAL COMMUNICATE CPU I /Ai TIMER EVENT INTERRUPTS INTERRUPTS CONTROL PARALLEL PORTS . COUNTERS ADDRESS DATA BUS AND 1/0 PINS FIGURE 2. Block diagram. i I I I I I I I I ,-. ESC FORM 193A JUL 91 Provided by IHSNot for

3、ResaleNo reproduction or networking permitted without license from IHS-,-,-I SMD-57b2-8777L 57 .SqSSSSb 00127LO W STATE 4 INTE ANAL GLOCK Pi IP2 XTAL E STATE 5 Pi IPZ m STATE 6 Pi 1 PZ m Clock waveforms L TESE SIGNALS ARE NOT ACTIVATED DWtING THE EXECUTXON OF A MOVX htE EXTERNAL PRbERAM MEMORY FETCH

4、 Ea I 1 PCL our1 . WPCL OUL I SAMPLED 1 -la rv CAMPLEU pano CYCLE I RD PGL bur F PRODAAEC HEMORY f!3 EXTERNAL) PO PZ INDICATES DPH OR P2 URITE CYCLE I .- -. - UR I PCL UT(EVEN IF PROIRAM MEMORY IS INTERNAL PO 1 DPL OR Ri - OUT 1 PS INDXCATEC OPH OR P2 SFR KI PCH TRANSITIONS OLD DATA I f!RT OPERATIUN

5、 PO PINS 6AHPLhI HOV PWIT, SRC NEW DATA HV DES1,PO HOV DS.BURT tpi,P2, P PO PINS IiAMPLED IiNCLUOES ZNTO, INTI. TO - Pi. P2, P3 PINS SAMPLED TNS Cr, PB.PB. SAMPLED txa I RXO SAMPLED (HWE This diagram indicates when signals are clocked internally. to the pins, however, ranges from 50 ns to 150 ns. su

6、ch as Temperature and pin Loading. component. 50 ns. specifications. The time it takes the signals to propagat This propagation delay is depehdent on variables Propagation also varies fom output to output and compbnent to Typically though, TA = 25Y, fully loaded) RO and WR propagation delays are app

7、roximatly The other signals are typically 85 ns. Propagation delays are incurporated in the ac FIGURE 3. Switchincl test circuit and waveforms. - -_ “_ - SPZE SW2-66Q9i -_ STANDARDIZED A MILITARY DRAWING r. l%ViIS?IrN LEVEL SbET fjEFEEtSE kLECTRONTCS SUPPLY CENTER 2 bAYTON, OHIO 45444 - - “,-. r6C F

8、ORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ALE REVISION LEVEL DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 - PSEN SHEET 13 MEMORY ACCESS Program tlemory Read Cycle (SEE NOTE 1 A7-AO -Q NSTR I e 4 -ADDRESS A15-AB x1 ADMIES

9、S Ai5-AB PORT AODR OR SFR-P2(sbalil be as te af cornpbimice and shSl.1 tb tunder $he riontrd1 cf $he accordance wizh :MIL-3-385?5, The burin-in $est circuit Me0.i ce manufatWei. s Technology .Review Board URE) in raccordamce :wih TUL-148535- b. hterim and final electrical test fpapirameterc shall $e

10、 as zp bc. AddiQional ecreening $or device class V ,beyond the *requiremenrs lof device -chss P .s;hFtlL be as specijied io appendix B of fiL-1-38535 ahd as etailed in Sable 118,herein. 4.3 aualif i cation i mspection. 6.3.T . 3Qudifiation inspectim -Tar ,lievice siasses B :and S shiill be MIL-ST-88

11、3nd herein for groups A, 3, C, D, and E inspecti $hail :be xhwe spcTf4be %hme Zcpeoified .in WLiI38535 .-and 4.4 ConfQrmanci inspection. Quality cohforrnance inspection .for *device dass M shall .be in amordance Mfh MfL-STD-88f (see 3.1 herein) ahd ias specified herein. Quality zonfo ?ir 13, and 5 :

12、sKal,L be those specified in method 51105 of MIL-CTD-883 and I (see 4.4.1 :through 4.4.51. Technokogy cotiformance inspectian far dasses Q .and;V shall he .in -accaFance ,inspetin for *device XcLasces SB anti *S es :cl, :for groups PI, 33, .C, fD, antl I Lincps? these tests shall have been graded in

13、 accordance with MIL-STD-883, test method 5012 (see 1.5 herein), The instruction set forms a part of the vendors test tape and shall be maintained and For device classes B and S, subgroups 7 and 8 tests shall For device classes Q and V, subgroups 7 and 8 shatl include verifying the functionality C.

14、Subgroup 4tC changes whichornay affect input capacitance. A minimum sample size of five devices with zero rejects shall be required. measurements) shall be measured only for the initial test and after process or design Provided by IHSNot for ResaleNo reproduction or networking permitted without lice

15、nse from IHS-,-,-SMD-5762-89971 59 W 9999996 00129L 2 W TABLE IIB. Additional screening for device class V. MIL-STD-883, test method . I Test IParticLe impact 2020 J noise detection I Internat visual Nondestructive 2023 or 2010, condition A or approved alternate I I Burn-rl Radioqraphi c I 201 2 101

16、5, total of 240 hdurs at t125Y . I Lot requirement L I 1 M)% 4.4.2 brup 8 jnspection. The group B inspection end-point electr5cal paPameters shalt be as specidkd 3n ;table IIA herein. 4.4.3 Group c inspection. the group 6 Snspectfon end-point electvieat :parameters sha24 be as specified II table ifA

17、 herein. 4.4.3.1 Additlanai critera T&r devli38 classes 8, 8, .and S. Steady-$tate %We test conditions5 mFthod 1005 o7 MIL-S1D-83: a. Te$t cohdjton C or D. the cert5Picate UP cornplSance. qual4 fying actlvi ty . Fer devTce class M, the test crcuii shall be submitted to DESC-CC for beview with For de

18、vSce classes El and S, the test circuit .shall be submStted to the b. TA = +125“C, minimum. c. best dura?ian: d. 4.4.32 XdditionaL crtera Yor .device classes Q and V. ?he $teatiy+rate 1Ste %st duration, Test wmdiltion and I,OOurc, except es permqtte By mefhod 1005 %sf :MIL-STD-883. All bviees sdlect

19、ed for kesting shall %e prNrammed rwith a chedk8rboard ?pattern (bP etpivalent. :Ahsr compleWn bf all testfng, the devhes shall be erased and verif5ed. tes.% Yemperdtef or approveif al.ternat?vec shall be as specWSed )in %he device manufacturer“t OM plah Yn taccordance wj$h HIL-8-38435. compl%anc$ a

20、nd chai1 be under %he control of the device manufacturers ?!a %I accwdance with WIL-l-385%. I IA heren. The sraady-state LWe Test *circuit shs1.l ,be stibmitted %o 4ESC-ECC with the cert 4.4.4 Group D incMction. The group b inspection end-point 4lectrical parameters shall fbe %a 3p&%1?&i Yn stable S

21、TANDARDIZED Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-c SIZE STANDARDIZED A MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL 4.4.5 Group E inspection. Group E inspection is required only for parts intended to

22、 be marked as radiation hardness assured (see 3.5 herein). device class M shall be M and D. level specified in the acquisition document. RHA levels for device classes B, S, Q, and V shall be R, D, R, and H and for RHA quality conformance inspection sample tests shall be performed at the RHA 5962-899

23、71 SHEET 21 a. b. C. d. e. f. 9. RHA tests for device classes B and S for levels M, D, R, and H or for device class M for Levels M and D shall be performed through each level to determine at what levels the devices meet the RHA requirements. These RHA tests shall be performed for initial qualificati

24、on and after design or process changes which may affect the RHA performance of the device. End-point electrical parameters shall be as specified in table IIA herein. Prior to total dose irradiation, each selected sample shall be assembled in its qualified package. It shall pass the specified group A

25、 electrical parameters in table I for subgroups specified in table IIA herein. For device classes M, B, and S, the devices shall be subjected to radiation hardness assured tests as specified in #1L-M-38510 for RHA level being tested, and meet the postirradiation end-point etectrical parameter limits

26、 as defined in table I at TA = t25OC 15 percent, after exposure. Prior to and during total dose irradiation testing, the devices shall be biased to establish a worst case condition as specified in the radiation exposure circuit. For device classes M, B, and S, subgroups 1 and 2 in table V, method 50

27、05 of MIL-STD-883 shall be tested as appropriate for device construction. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied. 4.5 Erasing procedure. The recommend d erasure procedure is exposure to ultraviolet light (at 2537 Angstroms) to 2 an integrat

28、ed dose of at least 15 W-c/cm rating for 20 to 30 minutes, at a distance of about 1 inch, should be sufficient. 4.6 Programming procedures. The used for programming the device: programming characteristi cs in table III and the following procedures shall be a. Connect the device in the electrical con

29、figuration (see figure 4) for programming. 4 and programming characteristics of table III shall apply. Initially and after each erasure, all bits are in the high “HI state. running with a 4 to 6 HHz oscillator. 1 and pins P2.CkP2.3 of port 2, while the data byte is applied to port O. be held low, an

30、d P2.7 and RCT high. EA/Vp is held normally high, and is pulsed to t21 V. normafly being held high, is pulsed low for 50 ms. The EA/Vpp is returned to high. The waveforms of figure To be programmed, the device must be The address of an EPROM location to be programmed is applied to port b. Pins P2.4-

31、P2.6 and PSEN should (These are all TTL levels except RST, which requires 2.5 V for high). While EA/Vpp is at 21 V, The ALE/PROG pin, which is Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-B97L 59 9999996 0012920 O Symbot Parameter I/ I Il

32、in J Max I Units I I I I %HSH hS lm high to Vpp SiZE STANDARDIZED A MILITARY DRAWING DEmN$E ELECTRONICS SUPPLY GENTER BATTON, OHIO 45444 SHGL - 5962-89971 REVISION LEVEL SHEET 22 I vPp setup to PROG I I O f I %HSL IVpp hold after I 1 PS I I I I %LGH width I I I I L !Address to data valid !%LCL ! ns

33、J I tAVQV I- %LQV IENABLE to data valid I %LCL I ns EHQZ Data float after ENABLE 1 O 48tCLCL 1 nc 1 I I/ The following conditions apply during programming and verification: a. vss = o v b. C. 2I0C S TC 27OC d. See figure 4 t4.5 V 5 Vcc 5 t5.5 V Provided by IHSNot for ResaleNo reproduction or network

34、ing permitted without license from IHS-,-,-EPROM Programming Security Bit Programming and Verification Waveforms NC NC PROGRAMMING VERIFICATION PI vcc p2.0- P2.3 PO 1 PI. O-PI -7 ADDRESS P2.0-P2.3 SIZE STANDARDIZED A MILITARY DRAWING I 21V *0.5V I 5962-89971 TTL HIGH 1-1 TTL HIGH -1 I I DATA OUT TTL

35、 HIGH -I F TTL HIGH +-EHQz TTL I 4-6 Security Bit Programming Configuration 4IGH 9 P2.4 P2.5 P2.6 P2.7 XTAL2 %TAL I vss ALE EA RST PSEN - - +5v NC - - ALE/PROG 50 ms PULSE TO GNO FIGURE 4. EPR0f.f programming configuration and waveforms. DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I REVISIO

36、N LEVEL I SHEET 23 I I I ESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SHD-59b2-8997L 59 999999b O032922 4 W P rqtrraimi ng verification ConS i gurat i on C5V - VCG PO PGM (USE DATA 1DK PUL Programming EonT i gurat ion P2.4 w,

37、I 4=6 MHZ XTALI TTC HIGH J- I - “h FIGURE 4, EPROM proqr,arnming .canfiqupatian mdwaveYorms - Continue& Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-i SIZE STANDARDIZED A 5. PACKAGING 5.1 Packaginq requirt=. The requirements for packaging shall be

38、 in accordance with MIL-M-38510 for device classes Il, 8, and S and MIL-1-38535 for device classes Q and V. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purpo

39、ses. contractor-prepared specif ication or drawing. 6.1.1 Replaceability. Microcircuits covered by this drawing will reptace the same generic device covered by a 6.1.2 Substitutability. 6.2 Configuration coiitrol of SMDs. Device classes B and Q devices will replace device class M devices. All propos

40、ed changes to existing SMDs will be coordinated with the users of record for the individual documents. accordance with MIL-STD-481 using DD Form 1693, Engineering Change Proposal (Short Form). when a system application requires configuration control and which SIIDS are applicable to that system. mai

41、ntain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DESC-ECC, telephone (513) 296-6022. This coordination will be accomplished in 6.3 Record of users. I*lilitary

42、and industrial users shall inform Defense Electronics Supply Center DESC Will 5962-89971 6.4 Comments. 296-8526. Commeiits on this drawing should be directed to DESC-ECC, Dayton, Ohio 45444, or telephone (513) 6.5 Symbols, definitions, and functional descriptions. Symbol Type Name and Description AD

43、O-AD7 I/O Port O (PO.0-PO.7): Port O is an 8-bit open drain bidirectional I/O port. address and data bus when using external memory. for data output during program verification. sink/source six LS TTL loads. It is also the multiplex low-order It is used Port O can I /o Port 1 (P1.0-P1.7): Port 1 is

44、an 8-bit quasi-bidirectional WO. It is used for the low-order address byte during program verification. loads. Port 1 can sink/source four LS TTL - RTS (P1.6) O Request-to-Send output: A low indicates that the device is ready to transmit. CTS (Pl .7) I Clear-to-Send input: A low indicates that a rec

45、eiving station is ready to receive. - I DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 1 REVISION LEVEL SHEET I 25 I I I ESC FORM 193A JUL 91 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-8997L 59 W 9999996 0032924 8.m SYmbal. Type A

46、B-AIS 1 iU 1.10 Name and Description Port tP2.GP2.7): Port 2 is an B-bJt quas9Lbjdirectional 110 port. accessfng external memory, address and the control signals durjng program verification. Bort 2 sinkleurce four LC TTL loads. Port 3 lP3.-P3.7): Port 3 is an +bit quasib.idirectonal U0 port. At alse

47、contains the interrupt, timer, serlal p?t, and RO and UR pins that are used by vaiGous optibns. hhe butput htkh corresponding to a secondary Tunctiun inus% be programmed to a une (1) for that funetion Po opi?ra.f& opt 3 &an sinkvsource four LS TTL loads. ln point-tu-point or mult3pbint contigurrtion

48、c, this pin contFoks the direction of pin P3.1. Serves 1s Receive batEl IhpuP 5n taop and diagnbstic mades. n point-to-point or multipoint configuratqonk, tR5s pin functibns as tiata inputPoutput. fn bop mode, ft servw as tPansmjt pin. A 18011 wrStten to this pYh enables diagnostic mode. Xnterkupt O input or gate cantto1 input for counter O. fntwrupt I iilpilt or gale cwtrol input Tor counter . Input t6 counter O. In addiY5on to f/, th5a pin prvvides inpiit to counter 7 or serves as SCLK (cerial clock) ihput. URIE: The write conlro