DLA SMD-5962-89551 REV B-2009 MICROCIRCUIT DIGITAL ADVANCED CMOS DUAL J-K POSITIVE EDGE-TRIGGERED FLIPFLOP MONOLITHIC SILICON.pdf
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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add vendor CAGE F8859. Add device class V criteria. Correct data limits in paragraph 1.3. Add case outline X. Add table III, delta limits. Update boilerplate to MIL-PRF-38535 requirements jak. 01-07-27 Thomas M. Hess B Update boilerplate paragrap
2、hs to the current MIL-PRF-38535 requirements. - LTG 09-05-01 Thomas M. Hess REV SHET REV B B SHET 15 16 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Marcia B. Kelleher CHECKED BY Ray Monnin DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, O
3、HIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY Michael A. Frye STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 89-02-06 MICROCIRCUIT, DIGITAL, ADVANCED CMOS, DUAL J-K POSITIVE EDGE-TRIGGERED FLIP- F
4、LOP, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-89551 SHEET 1 OF 16 DSCC FORM 2233 APR 97 5962-E288-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89551 DEFENSE SUPPLY CENTER
5、 COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes
6、 are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following examples. For device classes M and Q: 5962 - 89551 01 E A Federal stock class designa
7、tor RHA designator (see 1.2.1) Device type (see 1.2.2)Case outline (see 1.2.4)Lead finish (see 1.2.5) / / Drawing number For device class V: 5962 - 89551 01 V X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead fin
8、ish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and
9、 are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54AC109 Dual J-K positive edge-triggered flip-flop 1.2.3 Device class designator.
10、The device class designator is a single letter identifying the product assurance level as listed below. Since the device class designator has been added after the original issuance of this drawing, device classes M and Q designators will not be included in the PIN and will not be marked on the devic
11、e. Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outlin
12、e(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 Flat pack X CDFP4-F16 16 Flat pack 2 CQCC1-N20 20 Square leadless chip carrier 1.2.5 Lead finish. The lead finish
13、is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89551 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO
14、 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) -0.5 V dc to VCC+0.5 V dc DC output voltage range (VOUT) . -0.5 V dc to VCC+0.5 V dc Input clamp current (IIK) (VINVCC). 20
15、 mA Output clamp current (IOK) (VOUTVCC) . 20 mA Continuous output current (IOUT) (VOUT= 0.0 to VCC) 25 mA Continuous current through VCCor GND 50 mA Storage temperature range (TSTG) . -65C to +150C Maximum power dissipation (PD): 500 mW Lead temperature (soldering, 10 seconds). +260C Thermal resist
16、ance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C 1.4 Recommended operating conditions. 2/ Supply voltage range (VCC) +3.0 V dc to +6.0 V dc 4/ Case operating temperature range (TC) -55C to +125C Input voltage range (VIN) 0.0 V dc to VCCOutput voltage range (VOUT). 0.0 V
17、 dc to VCCInput rise or fall time (tr, tf): VCC= 3.6 V to 5.5 V . 0 to 8.0 ns/V Minimum setup time, Jn, Kn, to CPn (ts): TC= +25C, VCC= 3.0 V 6.5 ns TC= +25C, VCC= 4.5 V 4.5 ns TC= -55C to +125C, VCC= 3.0 V 8.0 ns TC= -55C to +125C, VCC= 4.5 V 5.5 ns Minimum hold time, Jn or Kn to CPn (th): TC= +25C
18、, VCC= 3.0 V 0.0 ns TC= +25C, VCC= 4.5 V 0.5 ns TC= -55C to +125C, VCC= 3.0 V 0.0 ns TC= -55C to +125C, VCC= 4.5 V 0.5 ns Minimum pulse width CPn, (tW): TC= +25C, VCC= 3.0 V 5.0 ns TC= +25C, VCC= 4.5 V 5.0 ns TC= -55C to +125C, VCC= 3.0 V 5.5 ns TC= -55C to +125C, VCC= 4.5 V 5.0 ns Minimum pulse wid
19、th CDn or SDn, (tW): TC= +25C, VCC= 3.0 V 6.0 ns TC= +25C, VCC= 4.5 V 5.0 ns TC= -55C to +125C, VCC= 3.0 V 8.0 ns TC= -55C to +125C, VCC= 4.5 V 5.5 ns Minimum recovery time CDn, SDn to CPn (trec): TC= +25C, VCC= 3.0 V 0.5 ns TC= +25C, VCC= 4.5 V 0.5 ns TC= -55C to +125C, VCC= 3.0 V 0.5 ns TC= -55C t
20、o +125C, VCC= 4.5 V 0.5 ns Maximum frequency CPn, (fMAX): TC= +25C, VCC= 3.0 V 85 MHz TC= +25C, VCC= 4.5 V 95 MHz TC= -55C to +125C, VCC= 3.0 V 65 MHz TC= -55C to +125C, VCC= 4.5 V 95 MHz 1/ Unless otherwise noted, all voltages are referenced to GND. 2/ The limits for the parameters specified herein
21、 shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 4/ Operation from 2.0 V dc to 3.0 V dc is p
22、rovided for compatibility with data retention and battery backup systems. Data retention implied no input transitions and no stored data loss with the following condition: VIH 70 percent VCC, VIL 30 percent VCC, VOH 70 percent VCCat 20 A, VOL 30 percent VCCat 20 A.Provided by IHSNot for ResaleNo rep
23、roduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-89551 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The f
24、ollowing specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturi
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