DLA DSCC-VID-V62 14604-2013 MICROCIRCUIT DIGITAL DUAL BUS BUFFER GATE WITH 3 STATE OUTPUTS MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY RICK OFFICER DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ Or

2、iginal date of drawing YY-MM-DD CHECKED BY RAJESH PITHADIA TITLE MICROCIRCUIT, DIGITAL, DUAL BUS BUFFER GATE WITH 3 STATE OUTPUTS, MONOLITHIC SILICON 13-12-18 APPROVED BY CHARLES F. SAFFLE SIZE A CODE IDENT. NO. 16236 DWG NO. V62/14604 REV PAGE 1 OF 14 AMSC N/A 5962-V015-14 Provided by IHSNot for Re

3、saleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14604 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance dual bus buffer gate with 3 state outputs m

4、icrocircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentatio

5、n: V62/14604 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVC2G126-EP Dual bus buffer gate with 3 state outputs 1.2.2 Case outline(s). The case outline(s) are as specified herein. Ou

6、tline letter Number of pins JEDEC PUB 95 Package style X 8 MO-187-CA Plastic small outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladiu

7、m E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14604 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 6.5

8、 V Input voltage range (VI) -0.5 V to 6.5 V 2/ Voltage range applied to any output in the high impedance or power off state (VO) -0.5 V to 6.5 V 2/ Voltage range applied to any output in the high or low state (VO) -0.5 V to VCC+ 0.5 V 2/ 3/ Input clamp current (IIK) (VI 0) -50 mA maximum Output clam

9、p current (IOK) (VO 0) . -50 mA maximum Continuous output current 50 mA maximum Continuous current through VCCor GND . 100 mA maximum Absolute maximum junction temperature range (TJ) -55C to +150C Storage temperature range (TSTG) -65C to +150C 1.4 Recommended operating conditions. 4/ 5/ Supply volta

10、ge range (VCC) Operating . 1.65 V to 5.5 V Data retention only . 1.5 V minimum High level input voltage (VIH): VCC= 1.65 V to 1.95 V 0.65 V x VCCminimum VCC= 2.3 V to 2.7 V 1.7 V minimum VCC= 3 V to 3.6 V . 2 V minimum VCC= 4.5 V to 5.5 V 0.7 V x VCCminimum Low level input voltage (VIL): VCC= 1.65 V

11、 to 1.95 V 0.35 V x VCCmaximum VCC= 2.3 V to 2.7 V 0.7 V maximum VCC= 3 V to 3.6 V . 0.8 V maximum VCC= 4.5 V to 5.5 V 0.3 V x VCCmaximum Input voltage range (VI) 0 V to 5.5 V Output voltage range (VO): High or low state 0 V to VCC3 - state 0 V to 5.5 V 1/ Stresses beyond those listed under “absolut

12、e maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extende

13、d periods may affect device reliability. 2/ The input negative voltage and output voltage ratings may be exceeded if the input and output clamp current ratings are observed. 3/ The value of VCCis provided in the recommended operating conditions table. 4/ All unused inputs of the device must be held

14、at VCCor GND to ensure proper device operation. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. Provided by IHSNot for R

15、esaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14604 REV PAGE 4 1.4 Recommended operating conditions - continued. 4/ 5/ High level output current (IOH): VCC= 1.65 V . -4 mA maximum VCC= 2.3 V -8 m

16、A maximum VCC= 3 V . -16 mA maximum -24 mA maximum VCC= 4.5 V -32 mA maximum Low level output current (IOL): VCC= 1.65 V . 4 mA maximum VCC= 2.3 V 8 mA maximum VCC= 3 V . 16 mA maximum 24 mA maximum VCC= 4.5 V 32 mA maximum Input transition rise or fall rate (t/V): VCC= 1.8 V 0.15 V, 2.5 V 0.2 V . 2

17、0 ns/V maximum VCC= 3.3 V 0.3 V . 10 ns/V maximum VCC= 5 V 0.5 V 5 ns/V maximum Operating virtual junction temperature range (TJ) -55C to +125C 1.5 Thermal characteristics. Thermal metric Symbol Case X Unit Thermal resistance, junction-to-ambient 6/ JA204.3 C/W Thermal resistance, junction-to-case (

18、top) 7/ JC(TOP)78 C/W Thermal resistance, junction-to-board 8/ JB83 C/W Characterization parameter, junction-to-top 9/ JT7.6 C/W Characterization parameter, junction-to-board 10/ JB82.6 C/W _ 6/ The thermal resistance, junction-to-ambient under natural convection is obtained in a simulation on a JED

19、EC standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. 7/ The thermal resistance, junction-to-case (top) is obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close description can be found in the ANSI SE

20、MI standard G30-88. 8/ The thermal resistance, junction-to-board is obtained by simulating in an environment with a ring cold plate fixture to control the printed circuit board (PCB) temperature, as described in JESD51-8. 9/ Characterization parameter, junction-to-top (JT) estimates the junction tem

21、perature of a device in a real system and is extracted from the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). 10/ Characterization parameter, junction-to-board (JB) estimates the junction temperature of a device in a real system and is extracted from

22、the simulation data for obtaining JA, using a procedure described in JESD51-2a (sections 6 and 7). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14604 REV PAGE 5 2. APPLIC

23、ABLE DOCUMENTS JEDEC Solid State Technology Association EIA/JESD 51-2a - Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air) EIA/JEDEC 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages EIA/JESD 51-8 - Integrated Circuits

24、 Thermal Test Method Environment Conditions Junction-to-Board JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org

25、) AMERICAN NATIONAL STANDARDS INSTITUTE ANSI SEMI STANDARD G30-88 - Test Method for Junction-to-Case Thermal Resistance Measurements for Ceramic Packages (Applications for copies should be addressed to the American National Standards Institute, Semiconductor Equipment and Materials International, 18

26、19 L Street, NW, 6 th floor, Washington, DC 20036 or online at http:/www.ansi.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESD

27、S identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as speci

28、fied in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal conn

29、ections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in figure 3. 3.5.4 Logic diagram. The logic diagram shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHS

30、Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14604 REV PAGE 6 TABLE I. Electrical performance characteristics. 1/ Test Symbol ConditionsTemperature, TJDevice type Limits Unit Min Max El

31、ectrical characteristics. High level output voltage VOHVCC= 1.65 V to 5.5 V, IOH= -100 A -55C to +125C 01 VCC 0.1 V VCC= 1.65 V, IOH= -4 mA 1.2 VCC= 2.3 V, IOH= -8 mA 1.9 VCC= 3 V, IOH= -16 mA 2.4 VCC= 3 V, IOH= -24 mA 2.3 VCC= 4.5 V, IOH= -32 mA 3.8 Low level output voltage VOLVCC= 1.65 V to 5.5 V,

32、 IOL= 100 A -55C to +125C 01 0.1 V VCC= 1.65 V, IOL= 4 mA 0.45 VCC= 2.3 V, IOL= 8 mA 0.3 VCC= 3 V, IOL= 16 mA 0.4 VCC= 3 V, IOL= 24 mA 0.55 VCC= 4.5 V, IOL= 32 mA 0.55 A or OE inputs IIVCC= 0 to 5.5 V, VI= 5.5 V or GND -55C to +125C 01 5 A Offset current IoffVCC= 0 V, VIor VO= 5.5 V -55C to +125C 01

33、 10 A Output impedance current IOZVCC= 3.6 V, VO= 0 to 5.5 V -55C to +125C 01 10 A Supply current ICCVCC= 1.65 V to 5.5 V, VI= 5.5 V or GND, IO= 0 -55C to +125C 01 10 A Delta supply current ICCVCC= 3 V to 5.5 V, one input at VCC 0.6 V, other inputs at VCCor GND -55C to +125C 01 500 A See footnotes a

34、t end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14604 REV PAGE 7 TABLE I. Electrical performance characteristics Continued. 1/ Test Symbol ConditionsTemperat

35、ure, TJDevice type Limits Unit Min Max Electrical characteristics - continued. Input capacitance, data inputs CIVCC= 3.3 V, VI= VCCor GND +25C 01 3.5 typical pF Input capacitance, control inputs CIVCC= 3.3 V, VI= VCCor GND +25C 01 4 typical Output capacitance COVCC= 3.3 V, VO= VCCor GND +25C 01 6.5

36、typical pF 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the abse

37、nce of specific parametric testing, product performance is assured by characterization and/or design. Switching characteristics. -55C TJ +125C Parameter From To VCC= 1.8 V VCC= 2.5 V VCC= 3.3 V VCC= 5 V Unit (input) (output) 0.15 V 0.2 V 0.3 V 0.5 V Min Max Min Max Min Max Min Max Propagation delay

38、(tpd) A Y 3.5 15 1.7 8.6 1.4 6.8 1 5.5 ns Enable time (ten) OE Y 3.5 15.2 1.7 8.6 1.5 6.8 1 5.5 ns Disable time (tdis) OE Y 1.7 12.6 1 5.7 1 4.5 0.1 3.3 ns Operating characteristics. TJ= +25C Parameter Test VCC= 1.8 V VCC= 2.5 V VCC= 3.3 V VCC= 5 V Unit conditions typical typical typical typical Pow

39、er dissipation Outputs enabled f = 10 MHz 19 19 20 22 pF capacitance Outputs disabled 2 2 2 3 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14604 REV PAGE 8 Case X FIGURE

40、1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14604 REV PAGE 9 Case X continued. Symbol Dimensions Inches Millimeters Min Max Min Max A .023 .035 0.60 0.9

41、0 A1 .000 .003 0.00 0.10 b .006 .009 0.17 0.25 c .005 NOM 0.13 NOM D .074 .082 1.90 2.10 E .086 .094 2.20 2.40 E1 .118 .125 3.00 3.20 e .019 BSC 0.50 BSC L .007 .013 0.20 0.35 NOTES: 1. Controlling dimensions are inch, millimeter dimensions are given for reference only. 2. Body length does not inclu

42、de mold flash or protrusion. Mold flash and protrusion shall not exceed 0.006 inch (0.15 mm) per side. 3. Falls within reference to JEDEC MO-187-CA. FIGURE 1. Case outline - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARI

43、TIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14604 REV PAGE 10 Device type 01 Case outline X Terminal number Terminal symbol 1 1OE 2 1A 3 2Y 4 GND 5 2A 6 1Y 7 2OE 8 VCCFIGURE 2. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license

44、from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14604 REV PAGE 11 Each buffer Inputs Output OE A Y H H H H L L L X Z H = High voltage level L = Low voltage level X = Dont care Z = Tri-state / floating FIGURE 3. Truth table. FIGURE 4. Logic diagram. Provided

45、by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14604 REV PAGE 12 FIGURE 5. Timing waveforms and test circuit. Provided by IHSNot for ResaleNo reproduction or networking permitted wi

46、thout license from IHS-,-,-DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/14604 REV PAGE 13 Notes: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Wa

47、veform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz and ZO= 50 . 4. The outputs are measured one at a time with one input transition per measurement. 5. tPLZand tPHZare the same as tdis. 6. tPZLand tPZHare the same as ten. 7. tPLHand tPHLare the same as tpd. 8. All parameters and waveforms are not applicable to all devic