DLA DSCC-VID-V62 08614-2008 MICROCIRCUIT DIGITAL CMOS 9-CHANNEL DIFFERENTIAL TRANSCEIVER MONOLITHIC SILICON《单片硅9通道差动收发器CMOS数字微电路》.pdf
《DLA DSCC-VID-V62 08614-2008 MICROCIRCUIT DIGITAL CMOS 9-CHANNEL DIFFERENTIAL TRANSCEIVER MONOLITHIC SILICON《单片硅9通道差动收发器CMOS数字微电路》.pdf》由会员分享,可在线阅读,更多相关《DLA DSCC-VID-V62 08614-2008 MICROCIRCUIT DIGITAL CMOS 9-CHANNEL DIFFERENTIAL TRANSCEIVER MONOLITHIC SILICON《单片硅9通道差动收发器CMOS数字微电路》.pdf(19页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONS LTR DESCRIPTION DATE APPROVED Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE 18 19 REV REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original
2、 date of drawing CHECKED BY Charles F. Saffle APPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITAL, CMOS, 9-CHANNEL DIFFERENTIAL TRANSCEIVER, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/08614 YY MM DD 08-04-02 REV PAGE 1 OF 19 AMSC N/A 5962-V021-08 Provided by IHSNot for ResaleNo r
3、eproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08614 REV PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 9-Channel differential transceiver microc
4、ircuit, with an operating temperature range of -55C to +125C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V6
5、2/08614 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN75976A-EP 9-Channel differential transceiver 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Num
6、ber of pins JEDEC PUB 95 Package style X 56 MO-153 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash pal
7、ladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08614 REV PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.3 V dc to +6 V dc
8、2/ Bus voltage range . -10 V dc to +15 V dc Data I/O and control (A side) voltage range -0.3 V dc to VCC+ 0.5 V dc Maximum receiver output current (IO) 40 mA Electrostatic discharge: B side and GND, Class 3, A 12 kV 3/ B side and GND, Class 3, B 400 V 3/ All terminals, Class 3, A. 4 kV All terminals
9、, Class 3, B. 400 V Storage temperature range (TSTG). -65C to 150C Continuous total power dissipation (PD): 4/ Case outline X: TA 25C 2500 mW TA= 70C 1600 mW Operating factor above TA= 25C. 20 mw/C 5/ Package thermal characteristics: Case outline X: Junction-to-ambient thermal resistance (RqJA). 50C
10、/W 6/ 7/ Junction-to-case thermal resistance (RJC). 27C/W 7/ Thermal-shutdown junction temperature (TJS) 165C 7/ 1.4 Recommended operating conditions. Supply voltage range (VCC) . 4.75 V dc to 5.25 V dc Minimum high level input voltage (VIH) (except nB+, nB-) . 2 V 8/ Maximum low level input voltage
11、 (VIL) (except nB+, nB-) 0.8 V 8/ Voltage at any bus terminal (separately or common-mode), (VO, VI, or VIC) (nB+ or nB-) . -7 V dc min to 12 V dc max 8/ Maximum high-level output current (IOH): Driver. -60 mA Receiver -8 mA Maximum low-level output current (IOL): Driver. 60 mA Receiver 8 mA Operatin
12、g free-air temperature range (TA). -55C to +125C 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
13、operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltage values are with respect to the GND terminals. 3/ This absolute maximum rating is tested in accordance with MIL-STD-883, method 3015.7. 4/ The maximum
14、 operating junction temperature is internally limited. 5/ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. 6/ Board-mounted, no air flow. 7/ This value is not a maximum limit, but a typical value based upon specified conditions. 8/ n = 1 9. P
15、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08614 REV PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Ap
16、plications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and
17、as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommen
18、ded operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall
19、be as shown in 1.2.2 and figure 1. 3.5.2 Logic diagram. The logic diagram shall be as shown in figure 2. 3.5.3 Terminal connections. The terminal connections shall be as shown in figure 3. 3.5.4 Function tables. The function tables shall be as shown in figure 4. 3.5.5 Timing waveforms and test circu
20、its. The timing waveforms and test circuits shall be as shown in figures 5a 5h. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/08614 REV PAGE 5 TABLE I. Electrica
21、l performance characteristics. 1/ Limits Test Symbol Conditions VCCTemperature, TA Device type Min Max Unit S1 to A, VT= 5 V See figure 5a. 0.7 Driver differential high-level output voltage VODHS1 to B, VT= 5 V See figure 5a. -55C to +125C 0.7 V S1 to A, VT= 5 V See figure 5a. +25C 0.7 S1 to B, VT=
22、5 V See figure 5a. 0.7 Driver differential low-level output voltage VODLS1 to A, VT= 5 V See figure 5a. -55C to +125C -0.8 V A side, VID= 200 mV, IOH= -8 mA See figure 5c. 4.75 V to 5.25 V -55C to +125C 4 High-level output voltage VOHB side, VT= 5 V See figure 5a. 5 V +25C 3 Typical V A side, VID= -
23、200 mV, IOL= 8 mA See figure 5c. 4.75 V to 5.25 V -55C to +125C 0.8 Low-level output voltage VOL B side, VT= 5 V See figure 5a. 5 V +25C 1 Typical V Receiver positive-going differential input threshold voltage VIT+IOH= -8 mA See figure 5c. -55C to +125C 0.2 V Receiver negative-going differential inp
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