DLA DSCC-VID-V62 05605 REV A-2011 MICROCIRCUIT DIGITAL IEEE 1394a-2000 OHCI PHY LINK LAYER CONTROLLER MONOLITHIC SILICON.pdf
《DLA DSCC-VID-V62 05605 REV A-2011 MICROCIRCUIT DIGITAL IEEE 1394a-2000 OHCI PHY LINK LAYER CONTROLLER MONOLITHIC SILICON.pdf》由会员分享,可在线阅读,更多相关《DLA DSCC-VID-V62 05605 REV A-2011 MICROCIRCUIT DIGITAL IEEE 1394a-2000 OHCI PHY LINK LAYER CONTROLLER MONOLITHIC SILICON.pdf(13页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 11-11-29 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE
2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, IEEE 1394a-2000 OHCI PHY/LIN
3、K LAYER CONTROLLER, MONOLITHIC SILICON YY MM DD 05-03-24 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/05605 REV A PAGE 1 OF 13 AMSC N/A 5962-V007-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBU
4、S COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05605 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance of an IEEE 1394a-2000 OHCI PHY/link layer controller microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Ite
5、m Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/05605 - 01 X E Drawing Device type Case outline Lead finish number (See 1.
6、2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Circuit function 01 TSB43AB23A-EP IEEE 1394a-2000 OHCI PHY/Link-layer controller 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 128 JEDEC MO-136 P
7、lastic quad flatpack 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other _ 1/ Users are cautioned to review th
8、e manufacturers data manual for additional user information relating to these devices. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05605 REV A PAGE 3 1.3 Absol
9、ute maximum ratings. 2/ Supply voltage range: REG18 -0.2 V to +2.2 V AVDD. -0.3 V to +4.0 V DVDD. -0.3 V to +4.0 V PLLVDD. -0.3 V to +4.0 V VDDP-0.5 V to +5.5 V Input voltage range for PCI, VI, PHY, and miscellaneous -0.5 V to VDD+0.5 V Output voltage range for PCI , VO, PHY and miscellaneous -0.5 V
10、 to VDD+0.5 V Input clamp current, (IIK) (VIVDD) 20 mA 3/ Output clamp current, (IOK) (VOVDD) 20 mA 4/ Electrostatic discharge . HBM: 2 kV 5/ Continuous total power dissipation . See dissipation rating table Operating ambient temperature range, (TA) : TSB43AB21AI . -40C to +85C Storage temperature r
11、ange, (TSTG) -65C to +150C Lead temperature 1.6 mm (1/16 inch) from cage for 10 seconds . +260C Dissipation Rating Table Case outline TAVDDI. For PCI use VI VDDP. 4/ Applies to external output and bi-directional buffers. For 5-V tolerant use VO VDDI. For PCI use VO VDDP. 5/ HBM is human body model.
12、6/ Standard JEDEC high-K board. 7/ Standard JEDEC low-K board. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05605 REV A PAGE 4 1.4 Recommended operating conditi
13、ons. Test condition Min Max Unit REG 18 1.6 2.0 V Core voltage, AVDD3.0 3.6 V Core voltage, DVDD3.0 3.6 V Core voltage, PLLVDD2.7 3.6 V Output voltage, VOTTL and LVCMOS terminals 0 DVDDV PCI I/O clamping voltage, VDDPVDDP = 3.3 V 3.0 3.6 V VDDP = 5.0 V 4.5 5.5 High level input voltage, VIH8/ PCI 3.3
14、 V 0.475VDDPVDDPV 5.0 V 2.0 VDDPPC(0-2) 0.7 DVDDDVDDRST_G 0.6 DVDDDVDDMiscellaneous 9/ 2.0 VDDPLow level input voltage, VIL8/ PCI 3.3 V 0 0.325VDDPV 5.0 V 0 0.8 PC(0-2) 0 0.2 DVDDRST_G 0 0.3 DVDDMiscellaneous 9/ 0 0.8 Input voltage, VIPCI 3.3 V 0 VDDPV Miscellaneous 9/ 0 VDDPOutput voltage, VO10/ PC
15、I 3.3 V 0 DVDDV Miscellaneous 9/ 0 DVDDInput transition time (trand tf), tt0 6 ns Operating ambient temperature, TARJA= 70.82 C/W 85 C Output current, IOTPBIAS outputs -5.6 1.3 mA Differential input voltage, VIDCable inputs, during data reception 118 260 mV Cable inputs, during arbitration 168 265 C
16、ommon-mode input voltage, VICTPB cable inputs, source power node 0.4706 2.515 V TPB cable inputs, nonsource power node 0.4706 2.015 11/ Maximum junction temperature, TJ128-PDT high-K JEDEC board, RJA= 74.6 C/W, PD= 0.312 W TA= 85C 105 C 128-PDT low-K JEDEC board, RJA= 101.3 C/W, PD= 0.229 W TA= 85C
17、105 C _ 8/ Applies to external inputs and bi-directional buffers without hysteresis. 9/ Miscellaneous terminals are: GPIO2(90), GPIO3 (89), SDA (92), SCL (91). 10/ Applies to external output buffers. 11/ For a node that does not source power; see section 4.2.2.2 in IEEE Std 1394a-2000. Provided by I
18、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/05605 REV A PAGE 5 1.4 Recommended operating conditions - Continued. Test condition Min Max Unit Power setup reset time, tpuRST_
19、G input 2 ms Receiver input jitter TPA, TPB cable inputs, S100 operation 1.08 ns TPA, TPB cable inputs, S200 operation 0.5 TPA, TPB cable inputs, S400 operation 0.315 Receiver input skew Between TPA and TPB cable inputs, S100 operation 0.8 ns Between TPA and TPB cable inputs, S200 operation 0.55 Bet
20、ween TPA and TPB cable inputs, S400 operation 0.5 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technolo
21、gy Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE) IEEE Standard 1394a-2000 - IEEE Standard for High Performance Serial Bus. (Copies of these documents are available online at http:/www.ieee.org or from the IEEE Serv
22、ice Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 088551331. 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identificatio
23、n (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.
24、4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections s
- 1.请仔细阅读文档,确保文档完整性,对于不预览、不比对内容而直接下载带来的问题本站不予受理。
- 2.下载的文档,不会出现我们的网址水印。
- 3、该文档所得收入(下载+内容+预览)归上传者、原创作者;如果您是本文档原作者,请点此认领!既往收益都归您。
下载文档到电脑,查找使用更方便
10000 积分 0人已下载
下载 | 加入VIP,交流精品资源 |
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- DLADSCCVIDV6205605REVA2011MICROCIRCUITDIGITALIEEE1394A2000OHCIPHYLINKLAYERCONTROLLERMONOLITHICSILICONPDF

链接地址:http://www.mydoc123.com/p-689202.html