DLA DSCC-VID-V62 04610 REV B-2012 MICROCIRCUIT DIGITAL FIXED POINT DIGITAL SIGNAL PROCESSOR MONOLITHIC SILICON.pdf

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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Correct lead finish on last page. Update boilerplate. - CFS 05-11-08 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 12-03-22 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLU

2、MBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV B B B B B PAGE 40 41 42 43 44 REV B B B B B B B B B B B B B B B B B B B B B B PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 REV STATUS OF PAGES REV B B B B B B B B B B B B B B B B B PAGE 1

3、2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Phu H. Nguyen DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Phu H. Nguyen TITLE MICROCIRCUIT, DIGITAL, FIXED POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON YY MM DD 04-04-08 APPROVED BY T

4、homas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04610 REV B PAGE 1 OF 44 AMSC N/A 5962-V045-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04610 REV B P

5、AGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Fixed-Point Digital Signal Processor microcircuit, with an operating temperature range of -40C to +100C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identif

6、ication. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04610 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). 1/ Device type Generic Circuit fun

7、ction 01 SM320VC5416-EP Fixed Point Digital Signal Processor 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins Package style X 144 Plastic ball grid array Y 144 Plastic quad flatpack 1.2.3 Lead finishes. The lead finishes are as specified below or other

8、lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other 1.3 Absolute maximum ratings. 2/ 3/ Supply voltage I/O range, (DVDD) . -0.3 V to +4.0 V Supply voltage core range, (CVDD) . -0.3 V t

9、o +2.0 V Input voltage range, (VI) . -0.3 V to +4.5 V Output voltage range (VO) . -0.3 V to +4.0 V Operating case temperature ranges, (TC): (Extended) . -40C to +100C Storage temperature range, (TSTG) -55C to +150C 1/ Users are cautioned to review the manufacturers data manual for additional user in

10、formation relating to this device. 2/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating cond

11、itions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to DVSS. 3/ Long term high temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of ov

12、erall device life. See manufacturer data for additional information on enhanced plastic packaging. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04610 REV B PAGE

13、 3 1.4 Recommended operating conditions. Device supply voltage, I/O (DVDD) +2.7 V to +3.6 V Device supply voltage, core (CVDD) (VC5416-160) +1.55 V to +1.65 V Device supply voltage, core (CVDD) (VC5416-120) +1.42 V to +1.65 V Supply voltage, GND (CVSS, DVSS) 0 V High level input voltage, I/O (VIH):

14、4/ (DVDD= 2.7 V to 3.6 V) 2.4 V to DVDD+ 0.3 V All other inputs 2.0 V to DVDD+ 0.3 V Low level input voltage, I/O (VIL): -0.3 V to +0.8 V Maximum high level output current, (IOH) . -8 mA 5/ Maximum low level output current, (IOL) . 8 mA 5/ Operating case temperature (TC) . -40C to +100C Junction to

15、air (RJA) Case X +38C/W Case Y +56C/W Junction to case (RJC) Case X +5C/W Case Y +5C/W 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or f

16、rom JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 4/ RS , INTn , NMI, X2/CLKIN, CLKMDn, BCLKRn, BCLKXn, HCS , 1HDS , 2HDS , HAS , TRST , BIO , Dn, An, HDn, TCK, DVDD= 2.7 V to 3.6 V 5/ Note that maximum output currents are DC values only. Transie

17、nt currents may exceed these values. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04610 REV B PAGE 4 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and

18、 legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (

19、if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are

20、as specified herein. 3.5 Diagrams. 3.5.1 Case outline(s). The case outline(s) shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2 . 3.5.3 Block diagram. The block diagram shall be as specified in figure 3. 3.5.4 Load circuit. Th

21、e load circuit shall be as specified in figure 4. 3.5.5 Timing waveforms. The timing waveforms shall be as shown in figure 5-24. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 1623

22、6 DWG NO. V62/04610 REV B PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Test condition -40C TC +100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max High level output voltage 2/ VOHDVDD= 2.7 to 3.0 V, IOH= Max 2.2 V DVDD= 3.0 to 3.6 V, IOH= Max

23、 2.4 Low level output voltage 2/ VOLIOL= Max 0.4 V Input current (VI= DVSSto DVDD) X2/CLKIN II-40 40 A TRST , HPI16 With internal pull down -10 800 HPIENA With internal pull down, RS = 0 -10 400 TMS, TCK, TDI, HPI 3/ With internal pull ups -400 10 A17:0, D15:0, HD7:0 Bus holder enabled, DVDD= Max 7/

24、 -275 275 All other input only pins -5 5 Supply current, core CPU IDDCCVDD= 1.6 V, fx= 160, 4/, TC= 25C 60 Typ 5/ mA Supply current .pins IDDPDVDD= 3.0 V, fx = 160 MHz, 4/, TC= 25C 40 Typ 6/ mA Supply current, standby IDLE2 IDDPLL x 1 mode, 20 MHz input 2 Typ mA IDLE3 Divide by two mode, CLKIN stopp

25、ed TC= 25C 1 Typ TC= 100C 30 Typ Input capacitance CI5 Typ pF Output capacitance CO5 Typ pF Input clock frequency fx10 8/ 20 9/ MHz See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, O

26、HIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04610 REV B PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test condition -40C TC+100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max CLOCK OPTION Divide by 2 and divide by 4 clock options

27、 timing requirements 10/ 11/ Cycle time, X2/CLKIN tc(CI)See figure 5 20 ns Fall time, X2/CLKIN tf(CI)4 Rise time, X2/CLKIN tr(CI)Pulse duration, X2/CLKIN low tW(CIL)4 Pulse duration, X2/CLKIN high tW(CIH)Divide by 2 and divide by 4 clock options switching characteristics 10/ 11/ Cycle time, CLKOUT t

28、c(CO)See figure 5 6.25 12/ 13/ ns Delay time, X2/CLKIN high/low to CLKOUT high/low td(CI-CO)4 11Fall time, CLKOUT tf(CO)1 TypRise time, CLKOUT tr(CO)TypPulse duration , CLKOUT low tW(COL)H-2 H-1Pulse duration , CLKOUT high tW(COH)H-2 H-1MULTIPLY BY N CLOCK OPTION (PLL ENABLED) Multiply by N clock op

29、tion timing requirements 11/ Cycle time, X2/CLKIN Integer PLL multiplier N (N = 1-15) 14/ tc(CI)See figure 6 20 200 ns PLL multiplier N = x.5 14/ 20 100 PLL multiplier N = x.25, x.75 14/ 20 50 Fall time, X2/CLKIN tf(CI)4 Rise time, X2/CLKIN tr(CI)Pulse duration, X2/CLKIN low tW(CIL)4 Pulse duration,

30、 X2/CLKIN high tW(CIH)Multiply by N clock option switching characteristics 11/ Cycle time, CLKOUT tc(CO)See figure 6 6.25 ns Delay time, X2/CLKIN high/low to CLKOUT high/low td(CI-CO)4 11Fall time, CLKOUT tf(CO)2 TypRise time, CLKOUT tr(CO)TypPulse duration , CLKOUT low tW(COL)H-2 H-1Pulse duration

31、, CLKOUT high tW(COH)H-2 H-1Transitory phase, PLL lock up time tp30 s See notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04610 REV B PAGE 7

32、 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test condition -40C TC+100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max MEMORY AND PARALLEL I/O INTERFACE TIMING Memory read timing requirements 12/ Access time, read data access from addr

33、ess valid, first read access 16/ ta(A)M1See figure 7 4H-9 ns Access time, read data access from address valid, consecutive read accesses 16/ ta(A)M22H-9Setup time, read data valid before CLKOUT low tsu(D)R7 Hold time, read data valid after CLKOUT low th(D)R0 Memory read switching characteristics 12/

34、 Delay time, CLKOUT low to address valid 16/ td(CLKL-A)See figure 7 -1 4 ns Delay time, CLKOUT low to MSTRB low td(CLKL-MSL) -1 Delay time, CLKOUT low to MSTRB high td(CLKL-MSH) 0 4 Memory write switching characteristics 12/ Delay time, CLKOUT low to address valid 16/ td(CLKL-A)See figure 8 -1 4 ns

35、Setup time, address valid before MSTRB low 16/ tsu(A)MSL2H-3 Delay time, CLKOUT low to data valid td(CLKL-D)W-1 4 Setup time, data valid before MSTRB high tsu(D)MSH2H-5 2H+6 Hold time, data valid after MSTRB high th(D)MSH2H-5 2H+6 Delay time, CLKOUT low to MSTRB low td(CLKL-MSL)-1 4 Pulse duration,

36、MSTRB low tw(SL)MS2H-3.2 Delay time, CLKOUT low to MSTRB high td(CLKL-MSH)0 4 I/O read timing requirements 17/ Access time, read data access from address valid, first read access 16/ ta(A)M1See figure 9 4H-9 ns Setup time, read data valid before CLKOUT low tsu(D)R7 Hold time, read data valid after C

37、LKOUT low th(D)R0 I/O read switching characteristics 17/ Delay time, CLKOUT low to address valid 16/ td(CLKL-A)See figure 9 -1 4 ns Delay time, CLKOUT low to IOSTRB low td(CLKL-IOSL) -1 4 Delay time, CLKOUT low to IOSTRB high td(CLKL-IOSH) 0 4 See notes at end of table. Provided by IHSNot for Resale

38、No reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04610 REV B PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test condition -40C TC+100C 1.55 V CVDD 1.65 V 2.

39、7 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max MEMORY AND PARALLEL I/O INTERFACE TIMING CONTINUED I/O write switching characteristics 17/ Delay time, CLKOUT low to address valid 16/ td(CLKL-A)See figure 10 -1 4 ns Setup time, address valid before IOSTRB low 16/ tsu(A)IOSL2H-3 Delay time,

40、CLKOUT low to write data valid td(CLKL-D)W-1 4 Setup time, data valid before IOSTRB high tsu(D)IOSH2H-5 2H+6 Hold time, data valid after IOSTRB high th(D)IOSH2H-5 2H+6 Delay time, CLKOUT low to IOSTRB low td(CLKL-IOSL)-1 4 Pulse duration, IOSTRB low tw(SL)IOS2H-2 Delay time, CLKOUT low to IOSTRB hig

41、h td(CLKL-IOSH)0 4 READY TIMING FOR EXTERNAL GENERATED WAIT STATES Ready timing requirements for external generated wait states 11/ 18/ Setup time, READY before CLKOUT low tsu(RDY)See figure 11-12 7 ns Hold time, READY after CLKOUT low th(RDY)0 Valid time, READY after MSTRB low 19/ tv(RDY)MSTRB 4H-6

42、.2Hold time, READY after MSTRB low 19/ th(RDY)MSTRB 4HValid time, READY after IOSTRB low 19/ tv(RDY)IOSTRB 4H-6 Hold time, READY after IOSTRB low 19/ th(RDY)IOSTRB 4H Delay time, CLKOUT low to MSC low td(MSCL) See figure 11-12 0 4 ns Delay time, CLKOUT low to MSC high td(MSCH)0 See notes at end of t

43、able. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04610 REV B PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test condition

44、 -40C TC+100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max HOLD AND HOLDA TIMINGS HOLD and HOLDA timing requirements 11/ Pulse duration, HOLD low duration tw(HOLD) See figure 13 4H+8 ns Setup time, HOLD before CLKOUT low 20/ tsu(HOLD) 7 HOLD and HOLDA switching char

45、acteristics 11/ Disable time, Address, PS , DS , IS high impedance from CLKOUT low tdis(CLKL-A)See figure 13 3 ns Disable time, R/ W high impedance from CLKOUT low tdis(CLKL-RW)3 Disable time, MSTRB , IOSTRB high impedance from CLKOUT low tdis(CLKL-S)Enable time, Address, PS , DS , IS valid from CLK

46、OUT low ten(CLKL-A)2H+3 Enable time, R/ W enabled from CLKOUT low ten(CLKL-RW)2H+3Enable time, MSTRB , IOSTRB enabled from CLKOUT low ten(CLKL-S)2 2H+3Valid time, HOLD low after CLKOUT low tv(HOLDA)-1 4 Valid time, HOLDA low after CLKOUT low -1 4 Pulse duration, HOLDA low duration tw(HOLDA)2H-3 See

47、notes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04610 REV B PAGE 10 TABLE I. Electrical performance characteristics - Continued. 1/ Test Sym

48、bol Test condition -40C TC+100C 1.55 V CVDD 1.65 V 2.7 V DVDD 3.6 V unless otherwise noted Limits Unit Min Max RESET, BIO , INTERRUPT, AND MP/ MC TIMINGS Reset, BIO interrupt, and MP/MC timing requirements 11/ Hold time, RS after CLKOUT low 20/ th(RS) See figure 14 2 ns Hold time, BIO after CLKOUT low 20/ th(BIO)