DLA DSCC-VID-V62 04602 REV E-2012 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf
《DLA DSCC-VID-V62 04602 REV E-2012 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf》由会员分享,可在线阅读,更多相关《DLA DSCC-VID-V62 04602 REV E-2012 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf(14页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add device case outline Y. Correct title. - CFS 03-12-08 Thomas M. Hess B Add new device type 02. Add new device case outlines Z and U. Update boilerplate to current revision. - CFS 04-08-24 Thomas M. Hess C Correct lead finishes on last page. - CFS 05-11-0
2、8 Thomas M. Hess D Add new device type 03. - CFS 06-11-01 Thomas M. Hess E Update boilerplate paragraphs to current requirements. - phn 12-02-14 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with AS
3、ME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV E E E E E E E E E E E E E E PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing YY-MM-DD CHECKED BY TOM HESS TITLE MICROCIRCU
4、IT, DIGITAL, ADVANCED BIPOLAR CMOS, 3.3-V 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS, MONOLITHIC SILICON 03-10-17 APPROVED BY RAYMOND MONNIN SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04602 REV E PAGE 1 OF 14 AMSC N/A 5962-V029-12 Provided by IHSNot for ResaleNo reproduction or networking permitted w
5、ithout license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04602 REV E PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 3.3-V ABT 16-bit bus transceiver with 3-state outputs microcircuit, with an
6、operating temperature range of -40C to +125C for device type 01, -40C to +85C for device type 02, and -55C to +125C for device type 03. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative co
7、ntrol number for identifying the item on the engineering documentation: V62/04602 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVTH16245A-EP 3.3-V ABT 16-bit bus transceiver with 3-s
8、tate outputs 02 SN74LVTH16245A-EP 3.3-V ABT 16-bit bus transceiver with 3-state outputs 03 SN74LVTH16245A-EP 3.3-V ABT 16-bit bus transceiver with 3-state outputs 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 48 JEDEC M
9、O-118 Plastic small-outline Y 48 JEDEC MO-153 Plastic small-outline Z 48 JEDEC MO-153 Plastic small-outline U 56 JEDEC MO-225 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Materia
10、l A Hot solder dip B Tin-lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04602 REV E PAGE 3 1.3
11、Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 4.6 V Input voltage range (VIN) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high impedance or power off state (VO) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high state (VO) -0.5 V to VCC+ 0.5 V
12、2/ Current into any output in the low state (IO): Device types 01 and 03 . 96 mA Device type 02 128 mA Current into any output in the high state (IO): Device types 01 and 03 . 48 mA 3/ Device type 02 64 mA 3/ Input clamp current (IIK) (VIVCC. 4/ The package thermal impedance is calculated in accorda
13、nce with JESD 51-7. 5/ All unused control inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG
14、 NO. V62/04602 REV E PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are
15、available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A.
16、Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating c
17、onditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outlines. The case outlines shall be as shown i
18、n 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Truth table. The truth table shall be as shown in figure 3. 3.5.4 Logic diagram. The logic diagram shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing wavefo
19、rms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04602 REV E PAGE 5 TABLE I. Electrical performance characterist
20、ics. 1/ Test Symbol Conditions 2/ VCCDevice type Limits Unit Min Max Input clamp voltage VIKII= -18 mA 2.7 V All -1.2 V High output voltage VOHIOH= -100 A 2.7 V to 3.6 V All VCC 0.2 V IOH= -8 mA 2.7 V All 2.4 IOH= -24 mA 3 V 01, 03 2 IOH= -32 mA 3 V 02 2 Low output voltage VOLIOL= 100 A 2.7 V All 0.
21、2 V IOL= 24 mA 2.7 V All 0.5 IOL= 16 mA 3 V All 0.4 IOL= 32 mA 3 V 02 0.5 IOL= 64 mA 3 V 02 0.55 Input current IIControl inputs, VI= VCCor GND 3.6 V All 1 A Control inputs, VI= 5.5 V 0 V or 3.6 V All 10 A or B ports, VI= 5.5 V 3/ 3.6 V All 20 A or B ports, VI= VCC3/ 3.6 V 01, 03 5 A or B ports, VI=
22、VCC3/ 3.6 V 02 1 A or B ports, VI= 0 V 3/ 3.6 V All -5 Input/output power-off leakage current IoffVIor VO= 0 to 4.5 V 0 V 02 100 A Input hold current II(hold)A or B ports, VI= 0.8 V 3 V All 75 A A or B ports, VI= 2 V -75 A or B ports, VI= 0 to 3.6 V 4/ 3.6 V 02 +500 -750 High output impedance power
23、up IOZPUVO= 0.5 V to 3 V OE = dont care 0 V to 1.5 V All 100 A Low output impedance power down IOZPDVO= 0.5 V to 3 V OE = dont care 1.5 V to 0 V All 100 A Supply current ICCOutputs high IO= 0, VI= VCCor GND 3.6 V All 0.19 mA Outputs low IO= 0, VI= VCCor GND 5 Outputs disabled IO= 0, VI= VCCor GND 0.
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