ANSI VITA 1.1-1997 VME64x《虚拟机环境VME64x》.pdf

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1、ANSI/VITA 1.1-1997 (R2003) American National Standard for VME64 Extensions Secretariat VMEbus International Trade Association Approved 1998, Reaffirmed 2003 American National Standards Institute, Inc. PO. Box 19658, Fountain Hills, AZ 85269 PH: 480-837-7486, FAX: Contact VITA Office E-mail: , URL: h

2、ttp:/ ANSI/VITA 1.1-1997 (R2003) American National Standard for VME64 Extensions Secretariat VMEbus International Trade Association Approved 1998, Reaffirmed 2003 American National Standards Institute, Inc. Abstract This standard is an extension of the ANSI/VITA 1-1994, VME64 Standard. It defines a

3、set of features that can be added to VME and VME64 boards, backplanes and subracks. These features include a 160 pin connector, a P0 connector, geographical addressing, voltages pins for 3.3V, a test and maintenance bus, and EMI, ESD, and front panel keying per IEEE 1101.10. American National Standa

4、rd Approval of an American National Standard requires verification by ANSI that the requirements for due process, consensus, and other criteria for approval have been met by the standards developer. Consensus is established when, in the judgment of the ANSI Board of Standards Review, substantial agr

5、eement has been reached by directly and materially affected interests. Substantial agreement means much more than a simple majority, but not necessarily unanimity. Consensus requires that all views and objections be considered, and that a concerted effort be made toward their resolution. The use of

6、American National Standards is completely voluntary; their existence does not in any respect preclude anyone, whether he has approved the standards or not, from manufacturing, marketing, purchasing, or using products, processes, or procedures not conforming to the standards. The American National St

7、andards Institute does not develop standards and will in no circumstances give an interpretation of any American National Standard. Moreover, no person shall have the right or authority to issue an interpretation of an American National Standard in the name of the American National Standard Institut

8、e. Requests for interpretations should be addressed to the secretariat or sponsor whose name appears on the title page of this standard. CAUTION NOTICE: This American National Standard may be revised or withdrawn at any time. The procedures of the American National Standards Institute require that a

9、ction be taken periodically to reaffirm, revise, or withdraw this standard. Purchases of American National Standards may receive current information on all standard by calling or writing the American National Standards Institute. Published by VMEbus International Trade Association PO Box 19658, Foun

10、tain Hills, AZ 85269 Copyright 1998, 2003 by VMEbus International Trade Association All rights reserved. No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without prior written permission of the publisher. NOTE: The users attention is called t

11、o the possibility that compliance with this standard may require use of one or more inventions covered by patent rights. By publication of this standard, no position is taken with respect to the validity of such claims or of any patent rights in connection therewith. The patent holders have, however

12、, filed a statement of willingness to grant a license under these rights on reasonable and non-discriminatory terms and conditions to applicants desiring to obtain such a license for use of this standard. Details may be obtained from the publisher. Printed in the United States of America - R1.2 ISBN

13、 1-885731-12-4 Table of Contents i ANSI/VITA 1.1-1997 (R2003) TABLE OF CONTENTS Foreword . v Chapter 1 1 Introduction to the VME64 Extensions standard 1 1.1 VME64 Extensions Objectives 1 1.1.1 9U Boards, Backplanes and Subracks . 2 1.2 Terminology . 2 1.3 References 2 1.3.1 Connector Notes . 2 1.4 S

14、tandard Terminology 3 Chapter 2 . 5 VME64x Compliance 5 2.1 Introduction . 5 2.2 Requirements . 5 2.2.1 6U VME64x Boards Minimum Features 5 2.2.2 3U VME64x Boards Minimum Features . 5 2.2.3 6U VME64x Backplanes Minimum Features 5 2.2.4 3U VME64x Backplanes Minimum Features 6 Chapter 3 . 7 P1/J1 & P2

15、/J2 160 Pin Connectors . 7 3.1 Introduction . 7 3.2 Requirements . 7 3.2.1 160 Pin Connector Placement 7 3.2.2 P1/J1 & P2/J2 Connectors, Rows z & d Pin Assignments . 7 3.2.3 Geographical Address Pin Assignments . 9 3.2.4 +3.3V Power . 10 3.2.5 V1/V2 Auxiliary Power . 11 3.2.6 VPC Power and Additiona

16、l +5V Power 11 3.2.7 Reset and ACFail 12 3.2.8 Board Power Dissipation 12 3.2.9 Backplane Termination Network using +3.3V Supply 12 3.2.10 Monolithic Backplanes . 13 3.2.11 Geographical Address Implementation . 13 3.2.12 Connector Pin Tail Lengths . 14 3.2.13 Labels on 96-pin Plug Connectors 14 3.2.

17、14 Backplane Connectors with Keying Devices 14 Chapter 4 17 P0/J0 Connector Area and VME64x Backplane Dimensions . 17 4.1 Introduction . 17 4.2 Requirements . 17 4.2.1 Connector Selection . 17 4.2.2 Custom Connectors . 18 4.2.3 P0/J0 Pin Definitions 18 4.2.4 P0/J0 Connector Mounting . 19 4.2.5 Pin C

18、urrent Ratings . 19 4.2.6 Backplane P0/J0 Keying 20 4.2.7 VME64x Backplane End Dimensions . 21 Chapter 5 . 23 EMC Front Panels and Subracks 23 Table of Contents ANSI/VITA 1.1-1997 (R2003) ii 5.1 Introduction . 23 5.2 Requirements . 23 5.2.1 EMC Front Panels and Subracks . 23 5.2.2 Solder Side Covers

19、 . 23 5.2.3 Front Panel Label Areas . 23 Chapter 6 25 Injector/Extractor Handles 25 6.1 Introduction . 25 6.2 Requirements . 25 6.2.1 Handles 25 6.2.2 Subracks 25 Chapter 7 27 Keying and Alignment Pin . 27 7.1 Introduction . 27 7.2 Requirements . 27 7.2.1 Subrack Keying 27 7.2.2 Board Keying . 27 7.

20、2.3 Keying Number Identification . 28 7.2.4 User Defined and User Installed 28 7.2.5 Multifunctional Alignment Pin . 28 Chapter 8 31 ESD and Front Panel Safety Ground Protection . 31 8.1 Introduction . 31 8.2 Requirements . 31 8.2.1 ESD Strips on VME64 Boards 31 8.2.2 ESD Clips in Card Guides and Su

21、bracks . 31 8.2.3 Solder Side Covers with ESD Protection 32 8.2.4 Front Panel Design for ESD Protection 32 8.2.5 Front Panel Safety Ground Protection 32 Chapter 9 33 Rear I/O Transition Boards 33 9.1 Introduction . 33 9.2 Requirements . 33 9.2.1 Mechanical Dimensions . 33 9.2.2 Mechanical Components

22、 33 9.2.3 Board Layout Orientation 34 9.2.4 Slot Keying Codes 34 9.2.5 Connector Pin Labeling 34 9.2.6 Increase in Backplane Height . 35 9.2.7 Power to Rear I/O Transition Board . 36 Chapter 10 37 Additions to CR/CSR Definition . 37 10.1 Introduction . 37 10.2 Requirements . 39 10.2.1 The Defined CR

23、 Area . 39 10.2.1.1 CR/CSR Space Specification ID 39 10.2.1.2 Module Characteristics Parameters 39 10.2.1.3 Interrupt Capabilities 40 10.2.1.4 Address Space Relocation . 41 10.2.1.4.1 Data Access Width ParameteRs (DAWPR) Definition 41 10.2.1.4.2 AM Capabilities Parameters (AMCAPs) . 42 Table of Cont

24、ents iii ANSI/VITA 1.1-1997 (R2003) 10.2.1.4.3 XAM Capabilities Parameters (XAMCAPs) 42 10.2.1.4.4 Address Decoder Masks (ADEMs) 43 10.2.1.5 Master Addressing Capabilities . 44 10.2.2 The Defined CSR Area . 45 10.2.2.1 Additions to the Bit Set and Bit Clear Registers . 45 10.2.2.2 Address Decoder co

25、mpaRe (ADER) Registers 47 10.2.3 The User CR Area . 48 10.2.4 The Configuration RAM (CRAM) Area . 49 10.2.5 The User CSR Area 50 10.2.6 Board Serial Number 51 Chapter 11 57 2eVME Protocol 57 11.1 Introduction . 57 11.1.1 2 Edge Handshakes . 57 11.1.2 Address Phases 57 11.1.3 Remapping the LWORD* Lin

26、e 57 11.1.4 Extended AM Codes . 57 11.1.5 Address Modes . 58 11.1.6 Known Length 2eVME Transfers 58 11.1.7 Slave Terminated 2eVME Transfers . 58 11.1.8 Slave Suspended 2eVME Transfers 59 11.1.9 Slave Error States 59 11.1.10 Master Terminated 2eVME Transfers . 59 11.1.11 2eBTO Bus Time Out Timer . 59

27、 11.2 Requirements . 59 11.2.1 Transceivers and Connectors . 59 11.2.2 Extended AM Codes . 60 11.2.3 Data Size 60 11.2.4 Protocols - General . 60 11.2.5 Address Phase Protocol and Timing . 61 11.2.6 Data Phase Protocol and Timing 62 11.2.7 2eBTO(x) Bus Time Out Timer 63 Appendix A . 79 Glossary of A

28、dditional VME64x Terms 79 Appendix B . 83 Additional VME64x Signal/Pin Descriptions 83 Appendix C . 85 VME64 and VME64x Function Mnemonics 85 Appendix D . 89 IEEE 1101.2-1992 Background . 89 Appendix E . 91 IEEE 1101.x Mechanical Feature References 91 List of Figures Figure 3-1 Backplane Termination

29、 Network using +3.3V Power . 15 Figure 4-1 P0 Connector Layout Position on VME64x Boards . 20 Figure 4-2 J0 Connector Layout Position on VME64x Backplanes . 21 Figure 4-3 VME64x Backplane Left and Right End Dimensions . 22 Table of Contents ANSI/VITA 1.1-1997 (R2003) iv Figure 5-1 Front Panel Label

30、Areas . 24 Figure 5-2 Injector/Extractor Handle Label Area 24 Figure 7-1 Keying Hole Positions and Associated Keying Codes 29 Figure 9-1 Front and Rear Board Orientation & Connector Pin Labeling 35 Figure 10-1 Structure of CR/CSR Space 38 Figure 11-1 2eVME Address Broadcast . 66 Figure 11-2 2eVME Ad

31、dress Broadcast - Slave Suspend Response 67 Figure 11-3 2eVME Address Broadcast - Slave Stop/Error Response . 68 Figure 11-4 2eVME Address Broadcast - Slave Suspend/Stop/Error Response . 69 Figure 11-5 2eVME Read Data Transfers - Master Termination 70 Figure 11-6 2eVME Read Data Transfers - Slave Su

32、spend . 71 Figure 11-7 2eVME Read Data Transfers - Slave Stop/Error on Odd Beat . 72 Figure 11-8 2eVME Read Data Transfers - Slave Stop/Error on Even Beat 73 Figure 11-9 2eVME Write Data Transfers - Master Termination . 74 Figure 11-10 2eVME Write Data Transfers - Slave Suspend . 75 Figure 11-11 2eV

33、ME Write Data Transfers - Slave Stop/Error on Odd Beat . 76 Figure 11-12 2eVME Write Data Transfers - Slave Stop/Error on Even Beat . 77 List of Tables Table 3-1 P1/J1 & P2/J2 Rows z & d Pin Assignments . 8 Table 3-2 Geographical Address Pin Assignments 10 Table 4-1 P0/J0/RJ0/RP0 Connector Contact L

34、abeling 19 Table 10-1 Slave Characteristics Parameter 40 Table 10-2 Master Characteristics Parameter 40 Table 10-3 Data Access Width Parameter (DAWPR) Definitions . 42 Table 10-4 Address Decoder Mask (ADEM) Definitions 43 Table 10-5 Address Relocation CR Examples . 44 Table 10-6 Bit Set Register Ass

35、ignment . 45 Table 10-7 Bit Clear Register Assignment 46 Table 10-8 Address Decoder compaRe (ADER) Register Definition . 47 Table 10-9 Address Relocation CR/CSR Examples 48 Table 10-10 CRAM_ACCESS_WIDTH Definition . 49 Table 10-11 Serial Number Example 51 Table 10-12 Defined Configuration ROM Assign

36、ments . 53 Table 10-13 Defined Control/Status Register (CSR) Assignments 55 Table 11-1 Extended Address Modifier Line Definition . 57 Table 11-2 6U 2eVME Extended Address Modifier Codes . 58 Table 11-3 3U 2eVME Extended Address Modifier Codes . 58 Table 11-4 6U VME64x Signal Field Definition 63 Tabl

37、e 11-5 3U VME64x Signal Field Definition 64 Table 11-6 2eVME Specific Timing Parameters . 64 Table 11-7 VME64 Timing Parameters . 65 Foreword v ANSI/VITA 1.1-1997 (R2003) Foreword This Foreword is not part of ANSI/VITA 1.1-1997 VME became the industrial bus of choice in the 80s with hundreds of manu

38、facturers supplying more than a thousand different boards to the world-wide market place. Thousands of customers utilized VME for a broad number of applications. In the late 80s, the VMEs draft standard was expanded for 64 bit data and address capability, which also doubled the throughput. Locks, Co

39、nfiguration ROM / Control & Status Registers (CR/CSR), rescinding DTACK*, auto system control detection, auto slot ID, plus optional shielded DIN connectors were also added. These additional features effectively transformed VME from an 80s bus to a 90s bus, which allows VME to be used in even more d

40、emanding applications for the early 90s. This standard is commonly referred to as VME64. In the summer of 1993 the VITA Standards Organization (VSO) agreed to publish the VME64 Standard. It was also agreed to use additional standards to add features as they are agreed upon by the VSO membership. Thi

41、s standard is a collection of additional features as agreed upon during 1994, 1995 and the first half of 1996. There will most likely be follow on standards with even more features. Features added to VME64 in this standard encompass twenty major areas: 1) “z“ and “d“ pin rows to the P1/J1 and P2/J2

42、connectors for 160 pins in each connector. 2) An optional 2 mm hard metric 95 signal pin plus 19 or 38 ground pins P0/J0 connector for more user defined I/O through the backplane. 3) Supply voltages of +3.3 and auxiliary volts, plus more +5V power 4) 35 more signal ground returns between VME64x boar

43、ds and VME64x backplanes for a total of 47 signal ground returns. 5) 46 more user defined I/O pins on the P2/J2 connector pair. 6) 14 bused spare pins and associated bused lines in the backplane, plus 2 unbused spare pins on the P1/J1 connector for future definition. 7) Pins allocated for a test and

44、 maintenance bus. 8) Slot geographical addressing. 9) Mechanical support for electromagnetic compatibility (EMC) control. 10) Mechanical support for electrostatic discharge (ESD) control. 11) Solder side covers with ESD protection. 12) An injection/extraction handle with a locking feature. 13) User

45、installed board to slot keying 14) Alignment pin which supports solid keying, improved connector alignment, front panel ESD protection and EMC gasket alignment. 15) Front Panel Safety Ground. 16) Reserved area on the front panel for attachment of ID and/or bar code labels. 17) Rear I/O transition bo

46、ards. 18) Added CR/CSR definition. 19) Supporting specifications for hot swap. 20) 2eVME: fast 2 edge protocol. Some of these features are independent of one another. Others are tied close together, such as the usage of +3.3 V which requires the new 160 pin connector for the P1 connector on VME64x b

47、oards and the usage of the VME64x backplane. If the 160 pin connector is Foreword ANSI/VITA 1.1-1997 (R2003) vi used on a VME64x board, the usage of 3.3 volt power, 48 volt power, hot swap control, serial bus, etc. are independent of one another. Wayne Fischer, Force Computers, was chair of the VSO

48、(VITA Standards Organization) task group that developed the draft for this standard. The following people participated in the ANSI canvass ballot. Malcolm Airst, MITRE Corporation Harry Andreas, Raytheon Systems Company Tom Baillio, Mercury Computer Systems, Inc. Ed Barsotti, Fermi Natl. Accelerator

49、 Lab Joe Bedard, Hewlett-Packard Company Drew Berding, Arizona Digital Martin Blake, VERO Electronics James Botte, Nortel John Bratton, VERO Electronics Gorky Chin, VISTA Controls Corporation Louis Costrell, NIST Dick DeBock, Matrix Corporation Robert Downing, J. J. Dumont, Framatome Connectors France Darrell Ferris, Boeing Wayne Fischer, Force Computers Lou Francz, Dialogic Corporation Stephen Guentner, Systran Corporation Michael Harms, Stanford Linear Accelerator Center Mike