Synthesis of Transaction-Level Models to FPGAs.ppt
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1、Synthesis of Transaction-Level Models to FPGAs,Prof. Jason Cong Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang VLSI CAD Lab Computer Science Department University of California, Los Angeles,Outline,Transaction-level model (TLM) SystemC TLM Metropolis Meta Model Synthesis from TLM RDR/MCAS: our exis
2、ting architectural synthesis approach xPilot: Ongoing synthesis infrastructure for TLM,Outline,Transaction-level model (TLM) SystemC TLM Metropolis Meta Model Synthesis from TLM RDR/MCAS: our existing architectural synthesis approach xPilot: Ongoing synthesis infrastructure for TLM,SystemC Framework
3、,SystemC history OO system/HW modeling and simulation SystemC under development by CAD vendors/researchers Synopsys Frontier Design CoWare (Belgium) Released to public Sept. 99 Open source distribution www.systemc.org Version 2 out July 01,Channels and Modules,Basic building blocks: Module (class) i
4、nstances, communicating via channel (class) instances Modules functionality coded as concurrent processes Processes communicate via channels or events,Communication Modeling in SystemC,Primitive Channels in SystemC Library,Ordinary signal (wire) of type Fill in data type T when instantiated Point-to
5、-point or multi-point (1 writer, n readers) Signal bus (arbitrary width) FIFO, for producer/consumer connection Pseudo-channels Mutex & semaphore, for interprocess sync Accessed using channel syntax Complex “hierarchical” channels composed of primitive channels, processes, modules,Events and Process
6、es,Events: abstract occurrences used for Process triggering (like VHDL sensitivity list) Channel communication Interprocess synchronization Process can call wait() to block on event Event occurrence tells simulator to schedule simulation of relevant process Processes execution Not called directly fr
7、om your code Triggered for simulation by events on ports, channels, or explicit named events Registered in constructor of enclosing module (associate method with events) Thread process infinite loop Must call wait() to lose control Method process runs to completion Less scheduling overhead,Data Type
8、s in SystemC,SystemC supports Native C/C+ Types SystemC Types SystemC Types Data type for system modeling 2 value (0,1) logic/logic vector 4 value (0,1,Z,X) logic/logic vector Arbitrary sized integer (Signed/Unsigned) Fixed Point types (Templated/Untemplated) Objective: to reflect HW registers & ALU
9、 operations,Functional Level and RTL Modeling in SystemC,Functional level Sequential, algorithmic, software-like Explore HW/SW architectures, proof of algorithms, performance modeling & analysisRegister transfer level Complete detailed functional description of hardware Every register, bus, bit for
10、every clock cycle Use C+ switch/case for FSM implementation At this point, can switch to HDL, but staying in SystemC leverages test benches Prepare for HW synthesis step by using only synthesizable constructs,Transaction Level Modeling in SystemC,Transaction level Model includes architectural compon
11、ents Maintain component interface accuracy E.g., buses modeled as channels (read/write operations) Behavioral style inside a component Simulates 100-10,000x faster than RTL Provide execution platform for SW development,TLM Raise the Level of Architectural Modeling,What is TLM?Communication uses func
12、tion calls burst_read(char* buf, int addr, int len); Why is TLM interesting? Simulation: Fast and compact Integrate HW and SW models Early platform for SW development Early system exploration and verification Verification reuse Synthesis Reference: www.systemc.org,Typical Design Flow Using TLM,Funct
13、ional model Captures system behaviourTLM, Transaction Level Model Bus transactions Accurate interaction with SW portion Simulates rapidly Can create TLM model initially,Introduction of Metropolis,A UCB and GSRC project, http:/www.gigascale.org/metropolis/ Platform-based design ASV Platforms have suf
14、ficient flexibility to support a series of applications/products Choose a platform by design space exploration Above two require models to be reusable Orthogonalization of concerns Computation vs. Communication Behavior vs. Coordination Behavior vs. Architecture Capability vs. Cost,Metropolis Meta M
15、odel,A combination of imperative program and declarative constraints Imperative program: objects (process, media, quantity, statemedia) netlist await block and label interface function call quantity annotation Declarative constraints Linear Temporal Logic (LTL) (synch) Logic of Constraints (LOC),A M
16、etropolis Design Tutorial,MyMapNetlist,A Metropolis Design Tutorial,MyMapNetlist,MyFncNetlist,M,P1,P2,Env1,Env2,B(P1, M.write) B(mP1, mP1.writeCpu); E(P1, M.write) E(mP1, mP1.writeCpu); B(P1, P1.f) B(mP1, mP1.mapf); E(P1, P1.f) E(mP1, mP1.mapf); B(P2, M.read) B(P2, mP2.readCpu); E(P2, M.read) E(mP2,
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