JEDEC JESD51-5-1999 Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment Mechanisms《带热感式附件部分的包装热测试板标准的扩充》.pdf

《JEDEC JESD51-5-1999 Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment Mechanisms《带热感式附件部分的包装热测试板标准的扩充》.pdf》由会员分享，可在线阅读，更多相关《JEDEC JESD51-5-1999 Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment Mechanisms《带热感式附件部分的包装热测试板标准的扩充》.pdf（9页珍藏版）》请在麦多课文档分享上搜索。

1、EIA/JEDECSTANDARDExtension of Thermal Test BoardStandards for Packages with DirectThermal Attachment MechanismsJESD51-5FEBRUARY 1999ELECTRONIC INDUSTRIES ALLIANCEJEDEC Solid State Technology AssociationNOTICEEIA/JEDEC standards and publications contain material that has been prepared, reviewed, anda

2、pproved through the JEDEC Board of Directors level and subsequently reviewed and approvedby the EIA General Counsel.EIA/JEDEC standards and publications are designed to serve the public interest througheliminating misunderstandings between manufacturers and purchasers, facilitatinginterchangeability

3、 and improvement of products, and assisting the purchaser in selecting andobtaining with minimum delay the proper product for use by those other than JEDEC members,whether the standard is to be used either domestically or internationally.EIA/JEDEC standards and publications are adopted without regar

4、d to whether or not theiradoption may involve patents or articles, materials, or processes. By such action JEDEC does notassume any liability to any patent owner, nor does it assume any obligation whatever to partiesadopting the EIA/JEDEC standards or publications.The information included in EIA/JED

5、EC standards and publications represents a sound approachto product specification and application, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby an EIA/JEDECstandard or publication may be further processed and ultimately bec

6、ome an ANSI/EIA standard.No claims to be in conformance with this standard may be made unless all requirements stated inthe standard are met.Inquiries, comments, and suggestions relative to the content of this EIA/JEDEC standard orpublication should be addressed to JEDEC Solid State Technology Assoc

7、iation, 2500 WilsonBoulevard, Arlington, VA 22201-3834, (703)907-7560/7559 or www.jedec.orgPublished byELECTRONIC INDUSTRIES ALLIANCE 1999Engineering Department2500 Wilson BoulevardArlington, VA 22201-3834“Copyright“ does not apply to JEDEC member companies as they arefree to duplicate this document

8、 in accordance with the latest revision ofJEDEC Publication 21 “Manual of Organization and Procedure“.PRICE: Please refer to the currentCatalog of JEDEC Engineering Standards and Publications or call Global EngineeringDocuments, USA and Canada (1-800-854-7179), International (303-397-7956)Printed in

9、 the U.S.A.All rights reservedPLEASE!DON”T VIOLATETHELAW!This document is copyrighted by the EIA and may not be reproduced withoutpermission.Organizations may obtain permission to reproduce a limited number of copiesthrough entering into a license agreement. For information, contact:Global Engineeri

10、ng Documents15 Inverness Way EastEnglewood, CO 80112-5704 or callU.S.A. and Canada 1-800-854-7179, International (303) 397-7956EXTENSION OF THERMAL TEST BOARD STANDARDS FORPACKAGES WITH DIRECT THERMAL ATTACHMENT MECHANISMS(From JEDEC Board Ballot JCB-98-93, formulated under the cognizance of the JC-

11、15.1 Committee onThermal Characterization.)1 Background Previous JEDEC standards 1-2 and other test board standards residing under the thermal measurementoverview document 3 have described design specifications for construction of thermal test boards. Thesespecifications were intended for convention

12、al leaded and leadless packages. They did not address packagesdesigned with the intention of direct thermal attachment to the test board such as deep downset packages orthermally tabbed packages. This specification provides additional design detail for use in developingthermal test boards with appli

13、cation to these package types. The design detail is in addition to and not inreplacement of the design specifications of those previous standards.This specification should be used in conjunction with the electrical test procedures described inJESD51-1, “Integrated Circuit Thermal Measurement Method

14、- Electrical Test Method (SingleSemiconductor Device),” 4, and JESD51-2, “Integrated Circuit Thermal Test Method EnvironmentalConditions - Natural Convection (Still Air),” 5.1.1 ReferencesJESD51-3, “Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.”JESD51-7, “High Effe

15、ctive Thermal Conductivity Test Board for Leaded Surface Mount Packages.”JESD51, “Methodology for the Thermal Measurement of Component Packages (Single SemiconductorDevice).”JESD51-1, “Integrated Circuit Thermal Measurement Method - Electrical Test Method (SingleSemiconductor Device).”JESD 51-2, “In

16、tegrated Circuit Thermal Test Method Environmental Conditions - Natural Convection(Still Air).”JEDEC Standard No. 51-5Page 22 ScopeThis specification provides for additional design geometries to be added to established thermal test boardstandards. The additions are only to allow testing of packages

17、that need direct thermal contact with thethermal test board. Boards designed with this specification are not to be used on packages that do notrequire direct thermal attachment to the test board.Following the intent of the previous test board specifications, this specification allows design of bothu

18、niversal test boards for a wide number of package geometries within a package family or for the design ofunique boards for single packages.3 Top Layer Trace Design3.1 For single package test board designsThe thermal attach pad on the test board will be made on the top trace layer. The attach pad wid

19、th andlength dimensions are to be no more than 1 mm greater than the corresponding width and length dimensionsof the thermal attachment structure. For example, if a thermal attachment area has an exposed area of 12mm x 12 mm on the bottom of a 28 mm x 28 mm package, the thermal attach pad will be no

20、 larger than 13mm x 13 mm. The array must not be smaller than the thermal attachment structure.3.2 For universal or nested test board designsThe thermal attach area is to be made of an array of 1.0 mm x 1.0 mm (+/- 0.08 mm) trace squaresseparated by 0.2 mm (+/- 0.08 mm) clearances as shown in figure

21、 1. The array is to be large enough toencompass the largest thermal attachment structure anticipated for use on the test board. The array mustnot be smaller than the thermal attachment structure. The array is to be positioned to maximize the numberof trace squares that overlap the packages thermal a

22、ttachment area.NOTES1 The trace pattern used for the thermal attachment area must not contact any traces soldered to leads.2 The Cu thickness of the thermal attach pad must be as specified by the general thermal test cardspecification documents.JEDEC Standard No. 51-5Page 34 Thermal Vias Thermal via

23、s are only allowed on multi-layer test boards. Thermal vias for single package test board designs will be spaced on a 1.2 mm x 1.2 mm grid.This maintains the same thermal via spacing as allowed for universal test boards. One thermal via will exist for each trace square of a thermal attach area for a

24、 universal test boarddesign. This thermal via will be centered within trace square. The thermal via diameter is 0.3 mm (+/- 0.08 mm).Figure 1 Trace array pattern for thermal attachment area showing1.0 mm x 1.0 mm trace squares seperated by 0.2 mm spaces. The thermal via must provide thermal contact

25、to the top buried plane in the multi-layer test boardonly. Thermal vias shall be plated to a minimum of 0.025 mm Cu thickness throughout the via barrel. Isolation Clearance Regions: Isolation clearance regions are required in the bottom buried plane forall thermal vias. An isolation clearance of no

26、less than 0.6 mm in diameter shall be used. Isolationclearance regions are to be designed such that no isolation region merges with another. This willleave the bottom buried plane continuous from an electrical and thermal standpoint.NOTE Dots represent 1thermal via per trace area1.0 mm0.2 mm1.0 mmJE

27、DEC Standard No. 51-5Page 45 Solder MasksSolder masking is optional, but when used, shall be kept clear of the thermal attachment area or array.6 Data PresentationTable 1 lists parameters specified in this document. The “User” column allows the user to input actualmeasured values from his/her test b

28、oards. This table shall be appended to the table from the PCBdescription specification when used.Table 1 Specified Parameters and Values Used.Specified Geometry Specification Value User1 Attachment Pad Size(single PCB)attach geometry size or lessthan 1 mm larger2 Attachment Array Size(nested PCB)size of largest attachgeometry3 Array Trace Square Size 1.0 mm x 1.0 mm4 Array Trace Spacing 0.2 mm5 Via Diameter 0.3 mm6 Via Spacing 1.2 mm7 Via Plating Thickness(Minimum)0.025 mm8 Isolation Clearance Diameter 0.6 mm9 Number of Vias to Top BuriedLayer10 Via Attached to Bottom TraceLayeroptional