JEDEC JESD235A-2015 High Bandwidth Memory (HBM) DRAM.pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD235ANOVEMBER 2015JEDECSTANDARDHigh Bandwidth Memory (HBM)DRAM(Revision of JESD235, October 2013)NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequent

2、ly reviewed and approved by the JEDEC legal counsel.JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selec

3、ting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles,

4、materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications.The information included in JEDEC standards and publications represents a sound approach to product spec

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8、the resulting material.PRICE: Contact JEDECPrinted in the U.S.A. All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by JEDEC and may not bereproduced without permission.For information, contact:JEDEC Solid State Technology Association3103 North 10th StreetSuite 240 SouthArling

9、ton, VA 22201-2107or refer to www.jedec.org under Standards-Documents/Copyright Information.JEDEC Standard No. 235APage 1HIGH BANDWIDTH MEMORY (HBM) DRAM(From JEDEC Board Ballot JCB-15-54, formulated under the cognizance of the JC-42.3 Subcommittee on DRAM Memories, under item number 1797.99F, Rev.

10、1.42.)1ScopeThe HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface arch

11、itecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates.2Features 2n prefetch architecture with 256 bits per memory read

12、 and write access BL = 2 and 4 128 DQ width + Optional ECC pin support/channel Legacy Mode and Pseudo Channel Mode Operation; (64 DQ width for Pseudo Channel Mode) Differential clock inputs (CK_t/CK_c) DDR commands entered on each positive CK_t, CK_c edge. Row Activate commands require two cycles. A

13、ll other commands are one cycle command. Semi-independent Row varies by device density/channel Bank Grouping supported 2K or 4K Bytes per page; varies by device density/channel DBIac support configurable via MRS Data mask for masking WRITE data per byte Self Refresh Modes I/O voltage 1.2 V DRAM core

14、 voltage 1.2 V, independent of I/O voltage Channel density of 1 Gb to 32 Gb Unterminated data/address/cmd/clk interfaces Temperature sensor with 3-bit encoded range outputJEDEC Standard No. 235APage 23 HBM DRAM Organization The HBM DRAM is optimized for high-bandwidth operation to a stack of multipl

15、e DRAM devices across a number of independent interfaces called channels. It is anticipated that each DRAM stack will support up to 8 channels. Figure 1 shows an example stack containing 4 DRAM dies, each die supporting 2 channels. Each die contributes additional capacity and additional channels to

16、the stack (up to a maximum of 8 channels per stack).Each channel provides access to an independent set of DRAM banks. Requests from one channel may not access data attached to a different channel. Channels are independently clocked, and need not be synchronous. 4 DRAM dies with 2 channels per die Op

17、tional Base “Logic” Die Channel 0 Channel 1Figure 1 General Overview of a DRAM Die Stack with ChannelsThe DRAM vendor may choose to require an optional interface die that sits at the bottom of the stack and provides signal redistribution and other functions. The vendor may choose to implement many o

18、f the logic functions typically found on DRAM die on this logic die. This standard does not explicitly require nor prohibit such a solution.The division of channels among the DRAM dies within a stack is left to the vendor. The example above, with the memory for two channels implemented on each die,

19、is not a required organization. Organizations are permitted where the memory for a single channel is distributed among multiple dies; however, all accesses within a single channel must have the same latency for all accesses. Similarly, vendors may develop products where each memory die can flexibly

20、support 1, 2, or 4 channels enabling 8-channel configurations with stacks of 2 to 8 dies while keeping all data for a given channel on one die.Since each channel is independent, much of this standard will describe a single channel. Where signal names are involved, families of signals belonging to a

21、given channel will have the suffix a, b, , h for channels a through h. If no suffix is present, the signal(s) being described are generic instances of the various per-channel signals.JEDEC Standard No. 235APage 33.1 Channel DefinitionEach channel consists of an independent command and data interface

22、. RESET, IEEE1500 test port and power supply signals are common to all channels. A channel provides access to a discrete pool of memory; no channel may access the memory storage for a different channel.Each channel interface provides an independent interface to a number of banks of DRAM of a defined

23、 page size. See Table 3.3.2 Summary of Per-Channel SignalsTable 1 outlines the signals required for each channel, and Table 2 adds global signals that are required once per HBM device. See also Table 75 for 15 additional global signals associated with the IEEE1500 test access port.Table 1 Single Cha

24、nnel Signal CountTable 2 Global Signal CountFunction # uBumps NotesData 128 DQ127:0Column Command/Address 8 8 bits C7:0Row Command/Address 6 6 bits R5:0DBI 16 1 DBI per 8 DQsDM 16 1 DM per 8 DQsPAR 4 1 PAR per 32 DQsDERR 4 1 DERR per 32 DQsStrobes 16 1 RDQS_t/RDQS_c, WDQS_t/WDQS_c per 32 DQsClock 2

25、CK_t/CK_cCKE 1 CKEAERR 1 AERRRedundant Data 8 RD7:0Redundant Row 1 RRRedundant Column 1 RCTotal 212Function # uBumps NotesReset 1 RESET_nTEMP2:0 3 TEMP2:0CATTRIP 1 Catastrophic Temperature SensorTotal 5JEDEC Standard No. 235APage 43.2.1 Legacy Mode and Pseudo Channel ModeHBM DRAM defines two mode of

26、 operation depending on channel density. The mode support is fixed by design and is indicated on bits 17:16 of the DEVICE_ID wrapper register.Legacy mode provides 256 bit prefetch per memory Read and Write access. Address bit BA4 is a “Dont Care” in this mode.Pseudo Channel mode divides a channel in

27、to two individual sub-channels of 64 bit I/O each, providing 128 bit prefetch per memory Read and Write access for each Pseudo channel. Both Pseudo channels operate semi independent: they share the channels row and column command bus as well as CK and CKE inputs, but decode and execute commands indi

28、vidually as illustrated in Figure 2. Address BA4 is used to direct commands to either to Pseudo Channel 0 (BA4 = 0) or Pseudo Channel 1 (BA4 = 1). Power-down and Self-Refresh are common to both Pseudo channels due to shared CKE pin. Array timings are calculated individually for each Pseudo channel.

29、For commands that are common to both Pseudo channels (PDE, PDX, SRE, SRX and MRS) it is required that the respective timing conditions are met by both Pseudo channels when issuing that command. Pseudo channel mode requires that burst length is set to 4. Both Pseudo channels also share the channels m

30、ode registers. All I/O signals of DWORD0 and DWORD1 are associated with Pseudo channel 0, and all I/O signals of DWORD2 and DWORD3 with Pseudo channel 1.CK_tCK_cDont CareColumn CommandRow CommandDDQ(63:0)(PS 0)1. PS 0 = pseudo channel 0 (BA4=0); PS 1 = pseudo channel 1 (BA4=1).2. RL = 1 is shown as

31、an example. Other timings parameters (tMRD, tRRD, tRAS, tRP, tRTP) are not to scale.3. Timing parameters like tRCD, tRRD, tRAS, tRP, tRTP apply independently for pseudo channels 0 and 1.4. Self refresh entry (SRE) requires that tRP is satisfied in both pseudo channels.ACTIVATE PS 0 ACTIVATE PS 1 ACT

32、IVATE PS 0 ACTIVATE PS 1RD PS 0 RD PS 0 RD PS 1PRE PS 0 SREtRRD (PS 0)tRCD (PS 0)tRRD (PS 1)tRCD (PS 1)tRAS (PS 0)PRE PS 1tRAS (PS 1)tRP (PS 0)tRP (PS 1)tRTP (PS 0)tRTP (PS 1)RLDaD Da+1 Da+2 Da+3DQ(127:64)(PS 1)Da Da+1 Da+2 Da+3 Db+1 Db+2Db Db+3BL4RL BL4Figure 2 Pseudo Channel Mode Operation3.2.2 Du

33、al Command InterfacesTo enable higher performance, HBM DRAMs exploit the increase in available signals in order to provide semi-independent row and column command interfaces for each channel. These interfaces increase command bandwidth and performance by allowing read and write commands to be issued

34、 simultaneously with other commands like activates and precharges. See Commands.JEDEC Standard No. 235APage 53.2.3 AddressingTable 3 HBM Channel AddressingNOTE 1 The burst order of a BL2 burst is fixed for Reads and Writes, and the HBM device does not assign a column address bit to distinguish betwe

35、en the first and second UI of a BL2 burst. A memory controller may internally assign such a column address bit but that column address bit is not transmitted on the colum address bus to the HBM device. Refer to Table 12 and Table 13 for burst order.NOTE 2 Page Size = 2COLBITS * (Prefetch_Size/8) whe

36、re COLBITS is the number of column address bits. Prefetch size and Page size are for the configuration without ECC bits.NOTE 3 In Pseudo channel mode, an additional address bit BA4 is provided for RAS and CAS commands to direct commands either to Pseudo Channel 0 (BA4=0) or Pseudo Channel 1 (BA4=1).

37、 See Command Truth Table.NOTE 4 The HBM device indicates the support of Legacy Mode and/or Pseudo Channel Mode in bits 17:16 of the DEVICE_ID Wrapper Data Register.NOTE 5 The “8 Gb 8-High” addressing is a specific configuration that is optimized for an HBM stack using 8 DRAM dies. The stack height o

38、f all other configuration is vendor specific.NOTE 6 The stack ID (SID) acts as a bank address bit in command execution. Specific AC timing parameters or variations on selected timing parameters may be linked to SID. Table 27 and Table 28 and the vendor datasheets should be consulted for details.3.2.

39、4 Bank GroupsThe activity within a bank group must be restricted to ensure proper operation of the device for HBM DRAMs operating at frequencies above a certain threshold fCKBG. The banks within a device are divided into four or eight bank groups. The bank group feature is configurable via MRS. The

40、assignment of banks to bank groups is shown in Table 4.Different timing parameters are specified depending on whether back-to-back accesses are within the same bank group or across bank groups at shown in Table 5.Channel Density Legacy Mode4Channel Density Pseudo Channel Mode4Notes1 Gb 2 Gb 4 Gb 2 G

41、b(1 Gbper PC)4 Gb(2 Gb per PC)8 Gb(4 Gb per PC)8 Gb 8-High5(4 Gb per PC)Prefetch Size (bits)256 256 256 256128 for PC256128 for PC256128 for PC256128 for PC2Row Address RA12:RA0 RA13:RA0 RA13:RA0 RA13:RA0 RA13:RA0 RA14:RA0 RA13:RA0Column Address CA5:CA0 CA5:CA0 CA5:CA0 CA5:CA0 CA5:CA0 CA5:CA0 CA5:CA

42、0 3Bank Address BA2:BA0 BA2:BA0 BA3:BA0 BA2:BA0 BA3:BA0 BA3:BA0 SID,BA3:BA03,6Page Size 2 KB 2 KB 2 KB 2 KB1 KB for PC2 KB1 KB for PC2 KB1 KB for PC2 KB1 KB for PC2Refresh 8K/32 ms 8K/32 ms 8K/32 ms 8K/32 ms 8K/32 ms 8K/32 ms 8K/32 msRefresh Period 3.9 us 3.9 us 3.9 us 3.9 us 3.9 us 3.9 us 3.9 usJED

43、EC Standard No. 235APage 6Table 4 Bank 8 BanksBA2:BA016 BanksBA3:BA032 BanksSID,BA3:BA0Bank Group AssignmentsTable 5 Command Sequences Affected by Bank GroupsNOTE 1 Parameters tRTPSand tRTPLapply only when READ and PRECHARGE go to the same bank; use tRTPSwhen Bank Groups are disabled, and tRTPLwhen

44、Bank Groups are enabled.0 Group A Group A Group A12 Group B34 Group C Group B Group B56 Group D78 N/A Group C Group C9101112 Group D Group D13141516 N/A Group E17181920 Group F21222324 Group G25262728 Group H293031Corresponding AC Timing ParameterBank Groups DisabledBank Groups EnabledCommand Sequen

45、ce Accesses to different bank groupsAccesses within the same bank groupNotesACTIVATE to ACTIVATE tRRDStRRDStRRDLWRITE to WRITE tCCDStCCDStCCDLREAD to READ tCCDStCCDStCCDLInternal WRITE to READ tWTRStWTRStWTRLREAD to PRECHARGE tRTPStRTPStRTPL1JEDEC Standard No. 235APage 74 InitializationTo power up a

46、nd initialize the HBM device into functional operation the sequence in section 4.1 must be followed. At any time after the power-up initialization, the HBM device may be reset using the sequence in section 4.2. A limited set of IEEE 1500 port instructions may be used within the initialization sequen

47、ces, as described in section 4.3.The interactions between HBM functional reset and the IEEE 1500 port reset are as follows (also see section , HBM DRAMs provide two separate test interfaces as described below:): Functional reset requires that the IEEE 1500 port also be reset. The IEEE 1500 port can

48、be reset at any time without impacting normal operation. The IEEE 1500 port may be brought out of reset and a limited set of instructions may be used after a minimum time after RESET_n has been deasserted. See section 4.3. If not needed, the IEEE 1500 port may be left in reset (WRST_n = LOW) during

49、normal operation.4.1 HBM Power-up and Initialization SequenceHBM device must be powered up and initialized in a predefined manner. The following sequence and timing must be satisfied for HBM power up and initialization sequence. Also refer to Figure 3.1. Apply power to the VDDC, VDDQand VPPsupplies. The VDDCsupply must be applied before or at the same time as VDDQ. The power supply ramp time between 300 mV and VDDCmust be less than or equal to tINIT0. During the power ramp, VDDC VDDQand (VDDC - VDDQ) 4 ?Figure 7 DBIac Algor