JEDEC JESD217-2010 Test Methods to Characterize Voiding in Pre-SMT Ball Grid Array Packages.pdf

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1、JEDEC STANDARD Test Methods to Characterize Voiding in Pre-SMT Ball Grid Array Packages JESD217 SEPTEMBER 2010 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level a

2、nd subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purc

3、haser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patent

4、s or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach

5、 to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with t

6、his standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid Stat

7、e Technology Association 2010 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE

8、: Please refer to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organiza

9、tions may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or call (703) 907-7559 JEDEC Standard No. 217 -i- Introduc

10、tion As ball grid array component pitch continues to decrease, the need to characterize solder voiding has become more significant. Solder void manifestation (type and/or sizes) has been used to determine process capability as a means of quality assurance during process transfer, and as indicators o

11、f process stability from in-line manufacturing monitors. This document describes how to characterize voids in solder spheres in ball grid array packages prior to surface-mount (SMT) reflow soldering. JEDEC Standard No. 217 -ii- JEDEC Standard No. 217 Page 1 TEST METHODS TO CHARACTERIZE VOIDING IN PR

12、E-SMT BALL GRID ARRAY PACKAGES (From Board Ballot JCB-10-56, formulated under the cognizance of the JC-14.1 Subcommittee on Reliability Test Methods for Packaged Devices.) 1 Scope This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-S

13、MPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures. Test methods can be applied to several types of ball grid array packages such as FCBGA, PBGA, CBGA, and CCGA with minimum 0.5 mm ball-to

14、-ball pitch and constructed with leaded and lead-free solder alloys. Guidelines for pre-SMT voids may not be sufficiently robust where ball grid array packages balls are assembled onto unfilled micro-via structures on package substrate land. Hence, the un-filled microvia construction (Figure 1-1a) i

15、s considered out-of-scope for this document, while filled via (Figure 1-1b) is within scope. Figure 1-1 Illustration of Un-filled Microvia (1-1a) out-of-scope vs. Filled Microvia (1-1b) in-scope of document JEDEC Standard No. 217 Page 2 2 Terms and definitions ball grid array (BGA) packages: A packa

16、ge in which the external connections to the package are made via a rectangular array of ball-type connections, all on a common plane. (Ref. definition per JESD22-B112.) CBGA: Ceramic ball grid array package. CCGA: Ceramic column grid array package. field of view: The area of the test sample under me

17、trology examination. flip chip ball grid array (FCBGA) package: A type of ball grid array (BGA) package which consists of facedown die (flip chip FC) on organic substrate of package. NOTE FCBGA packages typically have a filled epoxy which is dispensed between the die and the substrate. leaded solder

18、: A solder sphere composed primarily of tin (Sn) and lead (Pb) elements. NOTE 67%/37% (SnPb) and 60%/40% (SnPb) are predominant formulations, and are commonly referred to as eutectic solder. lead free solder: A solder sphere which does not contain lead (Pb). NOTE Refer to J-STD-609 for leaded and le

19、ad free marking. PBGA: Plastic ball grid array package. Printed Circuit Board (PCB): Printed board that provides both point-to-point connections and printed components in a predetermined arrangement on a common base (also sometimes termed Printed Wiring Board). (Ref. IPC-T-50G) SAC: A type of lead-f

20、ree solder made from tin, silver, and copper (Sn=S,Ag=A, Cu=C). (Ref. IPC-7095B) surface mount process technology (SMT): A method of constructing electronic printed circuit boards in which components (small or large devices) are placed onto solder paste (or flux) in specified locations and exposed t

21、o reflow process window with varying sets of elevated temperature and time that allows solder coalescence and metallization. solder void area: The area of the solder void region within the X-ray image of a BGA solder ball or joint. JEDEC Standard No. 217 Page 3 3 Informative reference documents J-ST

22、D-609, Marking and Labeling of Components, PCBs, and PCBAs to Identify Lad (Pb) Pb-Free and Other Attributes JESD16-A, Assessment of Average Outgoing Quality Levels in Parts Per Million (PPM) JESD47, Stress-Test-Driven Qualification of Integrated Circuits JESD22-B112, Package Warpage Measurement of

23、Surface-Mount Integrated Circuits at Elevated Temperature IPC-A-610D, Acceptability of Printed Circuit Assemblies IPC-7095B, Design and Assembly Process Implementation for BGAs IPC-T-50G, Terms and Definition for Interconnecting and Packaging Electronic Circuits JEDEC Standard No. 217 Page 4 4 Ball

24、attach process flow Solder balls are attached by applying a flux/paste material on to the BGA pads, placing the solder balls on the pads, and reflowing the BGA package. The reflow process forms a metallurgical joint between the solder ball and the substrate ball pad. Alignment is a key parameter dur

25、ing ball placement to avoid missing solder balls or solder balls bridging. Figure 4-1 gives a sequential representation of the BGA ball attach process flow. Figure 4-1 BGA ball attach process flow diagram JEDEC Standard No. 217 Page 5 5 Types of solder voids For the sake of completeness, all six typ

26、es of voids observed in solder joints are described in this section, including potential voids that manifest after BGA type package are mounted onto a board. The individual characteristics of each of these voids are listed below. Macrovoids are the most common voids in solder joints. These are cause

27、d by volatile compounds that evolve during the soldering processes. These macrovoids generally do not affect the solder joint reliability unless they are present at interfacial regions in the solder joints where cracks typically propagate. This type of voids is within scope of this document. Planar

28、Microvoids are a series of small voids, in relatively the same plane, located at the interface between the PCB lands and the solder. These are caused by copper caves predominantly observed under immersion silver (ImAg) surface-finish coated lands. They do not affect initial product quality, but can

29、affect long term solder joint reliability. They can be eliminated by strict control of the ImAg surface finish plating and etching materials and critical process parameters. Shrinkage Voids are caused by the shrinkage during solidification, mostly for SAC and other lead free solders. They do not gen

30、erally appear near the solder-to-PCB land interface and do not impair the solder joint reliability. These shrinkage voids can be minimized by increasing the cooling rate during soldering and avoiding disturbance to the joint while its solidifying. Micro-via Voids are caused by the presence of micro-

31、vias designed in the PCB lands. Large micro-via voids, if located in solder joints in high stress areas of a package can impact solder joint reliability. Plating the micro-via shut, or filling it completely with solder paste by double printing can minimize the creation of these voids. IMC Microvoids

32、 occur within the intermetallic compound (IMC) formed between copper and high Sn solders, including SAC and SnPb solders. These IMC microvoids do not form immediately after the soldering process, but after aging at high temperatures or during temperature cycling of the solder joints. The true root c

33、ause is still under investigation, but a Kirkendall voiding mechanism may play a part. These voids can affect solder joint reliability, particularly in instances when brittle fracture is initiated within the IMC during drop or mechanical shock to the solder joint. Pinhole Voids are caused by pinhole

34、s in the copper lands of the PCB. With sufficient quantity, they can affect solder joint reliability. These voids are caused by entrapped PCB fabrication chemicals within these pinholes that volatilize during the reflow soldering process. The pinholes occur due to an excursion within the copper plat

35、ing process at the PCB fabricator and can be eliminated by improved copper plating process control systems. These type of voids are considered out-of-scope JEDEC Standard No. 217 Page 6 5 Types of solder voids (contd) Figure 5-1 illustrates all six types of voids and their typical size and location

36、in a BGA solder joint. Figure 5-1 Typical size and location of various types of voids in a BGA solder joint For this publication, focus is placed on macrovoids, because they are most likely to manifest prior to SMT process and can be identified by most metrologies. The other type of voids is noted f

37、or completeness, but out-of-scope due to metrology detection and void formation concerns. 6 Solder void metrologies 6.1 2-D X-ray 2-D X-ray is one of the metrologies being used to detect and measure the voids in BGA solder joints. There are a variety of 2-D X-ray tool vendors. Care must be taken to

38、optimize the tool settings to achieve the best possible measurements. Generic guidelines for this technique are described below. JEDEC Standard No. 217 Page 7 6.1 2-D X-ray (contd) 6.1.1 Tool requirement/limitation The X-ray tube should be perpendicular to the test sample during image capture, as sh

39、own in Figure 6-1. Oblique viewing does not provide “true” void %. The field of view may be modulated by adjusting the distance between the test sample and X-ray tube. Field of view ought to be set considering accuracy of the inspection as well as throughput requirements. Variations in the field of

40、view that permits 3x3, 4x4 and 5x5 ball array are commonly reported. Figure 6-1 Illustration of X-ray setup and its orthogonal alignment to test sample To achieve the best possible contrast between BGA voids and the surrounding area for solder void detection, adjustments to the grey scale should be

41、considered. Below are ranges of settings that may be utilized as starting points. The settings are given in terms of % grey scale (black is 0, white is 100): Solderball = 36 to 48 % Background = 85 to 100 % The above settings can be achieved by adjusting the current and voltage on the X-ray tool. Fi

42、gure 6-2 emphasizes the importance of proper contrast; voids are barely visible in the left image, while the right image was collected after achieving the best possible contrast. JEDEC Standard No. 217 Page 8 6.1 2-D X-ray (contd) 6.1.1 Tool requirement/limitation (contd) (0% contrast) (30% gray) Fi

43、gure 6-2 Example of contrasting in grey scaling (0% to 30% gray) permitting detection of solder voids In general, 2-D X-ray metrology provides some advantages such as general availability, ease of operation, non-destructive nature to test samples, and faster throughput over other techniques like 3-D

44、 X-ray and cross-section. However, it has some limitations which are given in Table 6-1. Table 6-1 2-D X-ray Potential limitations Item Image Plated Thru Hole via interference. The red squares in the image at the right indicate where the software algorithm for automatic void calculation has incorrec

45、tly identified via hole outlines that intersect the BGA ball outline as solder voids. This results in an over-estimation of the cumulative % void area within the BGA ball from the X-ray image. Interference of passive devices (like capacitors) with BGA solder joints. The software algorithm for automa

46、tic void calculation did not identify and measure the voids in the solder ball images that intersect the chip capacitor image within the figure at the right. JEDEC Standard No. 217 Page 9 6.1 2-D X-ray (contd) 6.1.1 Tool requirement/limitation (contd) Table 6-1 2-D X-ray Potential limitations (contd

47、) Item Image Before Measurement Image After Measurement The entire void area is not being measured by the automated software algorithm. Edge areas in the solder ball image are incorrectly being measured as voids in the ball image. Voids in the edge areas of the solder ball image are being missed dur

48、ing measurement by the automated software algorithm. Some of the limitations can be attributed to software algorithms provided with the tools, while others are dependent on the type and location of solder voids or inherent to 2-D transmission X-ray technology itself. Nevertheless, 2-D X-ray metrolog

49、y can be used in conjunction with stand-alone image analysis software applications. 6.2 3-D computer tomography X-ray 3-D- X-ray tomography can be used as an engineering tool to image, measure and locate solder joint voids. Tomography imaging involves three main steps: 1) Image acquisition (collect shadow images as the sample rotates through at least 180 degrees). 2) Software reconstruction that renders the 3-D volume 3) Inspection where the size, shape, location and dimensions of the solder joint may be established and measured. Figure 6-3 shows the