JEDEC JESD204B 01-2012 Serial Interface for Data Converters.pdf

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1、JEDEC STANDARD Serial Interface for Data Converters JESD204B.01 (Revision of JESD204B, July 2011) JANUARY 2012 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level a

2、nd subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purc

3、haser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patent

4、s or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach

5、 to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with t

6、his standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternati

7、ve contact information. Published by JEDEC Solid State Technology Association 2012 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not

8、to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies

9、 through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards and Documents for alternative contact information. JEDEC Standard No. 204B.01 Page

10、1 SERIAL INTERFACE FOR DATA CONVERTERS (From JEDEC Board Ballot JCB-08-01 and JCB-11-47, formulated under the cognizance of JC-16 Committee on Interface Technology.) 1 Scope This specification describes a serialized interface between data converters and logic devices. It contains normative informati

11、on to enable designers to implement devices that communicate with other devices covered by this specification. Informative annexes are included to clarify and exemplify the specification. Due to the range of applications involved, the intention of the document is to completely specify only the seria

12、l data interface and the link protocol. Certain signals common to both the interface and the function of the device, such as device clocks and control interfaces, have application-dependent requirements. Devices may also have application-dependent modes, such as a low power / shutdown mode that will

13、 affect the interface. In these instances, the specification merely constrains other device properties as they relate to the interface, and leaves the specific implementation up to the designer. Revision A of the standard was expanded to support serial data interfaces consisting of single or multipl

14、e lanes per converter device. In addition, converter functionality (ADC or DAC) can be distributed over multiple devices: All parallel running devices are implemented or specified to run synchronously with each other using the same data format. Normally this means that they are part of the same prod

15、uct family. Revision B of the standard now supports the following additional functions: Mechanism for achieving repeatable, programmable deterministic delay across the JESD204 link. Support for serial data rates up to 12.5 Gbps. Transition from using frame clock as the main clock source to using dev

16、ice clock as the main clock source. Device clock frequency requirements offer much more flexibility compared to requiring a frame clock input. The logic device (e.g. ASIC or FPGA) is always assumed to be a single device. Figure 1 compares the scope of the original JESD204 specification and its revis

17、ions. JEDEC Standard No. 204B.01 Page 2 1 Scope (contd) 1 lane,1 linkMconvertersLogic Device (FPGA or ASIC)Logic Device (FPGA or ASIC)Mconverters1 link,L lanesMconvertersOne multipoint link.All lanes aligned.Similar convertersJESD204 revision AOriginal JESD204 version 20061 link,L lanesFrame clockFr

18、ame clockFrame clockFrame clockLogic Device (FPGA or ASIC)Mconverters1 link,L lanesMconvertersOne multipoint link.All lanes aligned.Similar convertersJESD204 revision B1 link,L lanesDevice clock 1Device clock 2Figure 1 Scope of original JESD204 and revisions A and B Although not illustrated in the f

19、igure, it is possible to apply multiple, independent instances of the JESD204 standard to the same device. JEDEC Standard No. 204B.01 Page 3 2 References 2.1 Normative The following normative documents contain provisions that, through reference in this text, constitute provisions of this standard. F

20、or dated references, subsequent amendments to, or revisions of, any of these publications do not apply. However, parties to agreements based on this standard are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated below. For undated ref

21、erences, the latest edition of the normative document referred to applies. 1. IEEE Std 802.3-2008, Part 3, Section Three, Local and metropolitan area networks - CSMA/CD access methods and Physical Layer specifications, 2008. http:/standards.ieee.org/getieee802/ 2. JEDEC JESD99, Terms, Definitions, a

22、nd Letter Symbols for Microelectronic Devices. 3. OIF-SxI-5-01.0, System Interface Level 5 (SxI-5): Common Electrical Characteristics for 2.488 3.125Gbps Parallel Interfaces, Optical Internetworking Forum, October 2002. 4. OIF-CEI-02.0, Common Electrical I/O- Electrical and Jitter Interoperability

23、agreements for 6G+ bps and 11G+ bps I/O, Optical Internetworking Forum, February 2005. 2.2 Informative The following standards contain provisions that, through references in the text, are informative in this standard. 5. ANSI T1.523-2001, ATIS Telecom Glossary 2000, February 2001. http:/www.atis.or

24、g/tg2k/ 6. IEEE Std 802.3-2008, Part 3, Section Four, Local and metropolitan area networks - CSMA/CD access methods and Physical Layer specifications, 2008. http:/standards.ieee.org/getieee802/ 7. ANSI/IEEE Std 91a-1991, Graphic symbols for logic functions, IEEE 1991, ANSI 1994. (Summary available a

25、t e.g. http:/en.wikipedia.org/wiki/Logic_gate) 8. INCITS 450-2009, Information technology - Fibre Channel - Physical Interface - 4 (FC-PI-4), available from http:/webstore.ansi.org 9. INCITS TR-35-2004 (R2009), Fibre Channel - Methodologies for Jitter and Signal Quality Specification (FC-MJSQ) , ava

26、ilable from http:/webstore.ansi.org JEDEC Standard No. 204B.01 Page 4 3 Terminology For the purposes of this standard, the terms and definitions given in JESD99 (reference 2) and the following apply: 3.1 Terms and definitions 8B/10B code: A DC-balanced octet-oriented data encoding specified in refer

27、ence 1, clause 36.2.4. (Ref. IEEE 802.3) ceil(x): The smallest integer greater than or equal to x. character: A symbol produced by 8B/10B encoding of an octet. NOTE 1 While all octets can be encoded as data characters, certain octets can also be encoded as control characters. NOTE 2 The same charact

28、er may exist as two different code groups, depending on running disparity. character clock: A signal used for sequencing the 8B/10B characters or octets. clock generator: A circuit used to generate synchronous, phase aligned device clocks to various devices in the JESD204B system. NOTE A clock gener

29、ator circuit can include one or more clock generator devices, but they must use a common source clock. code group: A set of ten bits that, when representing data, conveys an octet. (Ref. IEEE 802.3) control interface: An application-specific interface used to pass information (usually status and con

30、trol information) between a converter device and a logic device and/or between a device and a higher layer application level. NOTE The details of the control interface are outside the scope of the serial interface described by this standard. conversion clock: A signal used to define the analog sampl

31、ing moments in a converter. NOTE Usually the conversion clock is the same as the sample clock, except in case of interpolating DACs or decimating ADCs, where the conversion clock is faster than the sample clock. In all cases, the conversion clock is derived from the device clock. converter: An analo

32、g-to-digital converter (ADC) or digital-to-analog converter (DAC). NOTE In this standard, a converter is assumed to interface via a single stream of digital samples. converter device: A component package containing one or more converters. NOTE This standard specifies the interactions between one log

33、ic device and one or more converter devices. JEDEC Standard No. 204B.01 Page 5 3.1 Terms and definitions (contd) data link: An assembly, consisting of parts of two devices and the interconnecting data circuit, that is controlled by a link protocol enabling data to be transferred from a data source t

34、o a data sink. (“terminal” replaced by “device” in ANSI T1.523-2001.) descrambler: The inverse of a scrambler. (Ref. ANSI T1.523-2001) NOTE The descrambler output is a signal restored to the state that it had when it entered the associated scrambler, provided that no errors have occurred. device clo

35、ck: A master clock signal from which a device must generate its local clocks. floor(x): The greatest integer less than or equal to x. frame: A set of consecutive octets in which the position of each octet can be identified by reference to a frame alignment signal. (Adapted from ANSI T1.523-2001.) NO

36、TE 1 The frame alignment signal does not necessarily occur in each frame. NOTE 2 In JESD204, a frame consists of F octets and is transmitted over a single lane. frame clock: A signal used for sequencing frames or monitoring their alignment. frame period: One period of the frame clock, i.e. the durat

37、ion of one frame. NOTE During one frame period, one frame is transmitted over each lane of a multilane link. idle mode: An operating mode used for a converter that is not currently sampling data. interconnect: The transmission path along which a signal propagates. (Synonym for “medium” in ANSI T1.52

38、3-2001.) invalid code group: A code group that is not found in the proper column of the 8B/10B decoding tables, according to the current running disparity. (Ref. IEEE 802.3) lane: A differential signal pair for data transmission in one direction. line clock: A signal used for sequencing the serial b

39、its on an electrical interface. link: Synonym for “data link”. local clock: A clock derived inside a device from the device clock and used in the implementation of the JESD204B link within the device. NOTE 1 It is possible to align a local clock to an external signal, e.g. SYSREF. NOTE 2 An internal

40、 copy of the device clock is not a local clock. JEDEC Standard No. 204B.01 Page 6 3.1 Terms and definitions (contd) logic device: A component package containing exclusively or primarily digital logic; e.g., an ASIC or FPGA. NOTE This standard specifies the interactions between one logic device and o

41、ne or more converter devices. max(x, y): The largest of x and y. min(x, y): The smallest of x and y. mod(x, y): The remainder after dividing x by y (x modulo y). multiframe: A set of consecutive frames in which the position of each frame can be identified by reference to a multiframe alignment signa

42、l. (Ref. ANSI T1.523-2001) NOTE 1 The multiframe alignment signal does not necessarily occur in each multiframe. NOTE 2 In JESD204, a multiframe consists of K frames and is transmitted over a single lane. multiframe clock: A signal used for sequencing multiframes or monitoring their alignment. multi

43、point link: A data communications link that interconnects three or more devices. (“terminal” replaced by “device” in ANSI T1.523-2001.) nibble: A group of four data bits. (Ref. IEEE 802.3) octet: A group of eight adjacent binary digits, serving as the input to an 8B/10B encoder or the output of an 8

44、B/10B decoder. receiver: A circuit attached to a lane for reconstructing a serial bit stream into time-aligned frames. NOTE A receiver consists of one physical layer block and one link layer block. receiver block: The combination of the receiver transport layer and all receiver link layer and physic

45、al layer blocks connected to a link. receiver device: A component package containing one or more receiver blocks. rising edge of a differential signal(P,N): The simultaneous transitions that occur when signal(P) changes from the low logic level to the high logic level and signal(N) changes from the

46、high logic level to the low logic level. running disparity: A binary parameter having a value of + or , representing the imbalance between the number of ones and zeros in a sequence of 8B/10B code-groups. (Ref. IEEE 802.3) sample: The instantaneous value of a signal measured or determined at a discr

47、ete time. (Adapted from ANSI T1.523-2001, “sampled data”.) NOTE In the context of JESD204, a sample is always the digital representation of a signal. JEDEC Standard No. 204B.01 Page 7 3.1 Terms and definitions (contd) sample clock: A signal used to define the sample boundaries within a frame. NOTE U

48、sually the sample clock is the same as the frame clock, except in cases where there are multiple samples per converter within a frame, where the sample clock is an integer multiple of the frame clock. In all cases, the sample clock is derived from the device clock. scrambler: A randomizing mechanism

49、 that is used to eliminate long strings of consecutive identical transmitted symbols and avoid the presence of spectral lines in the signal spectrum without changing the signaling rate. (Ref. IEEE 802.3) source clock: An oscillator from which the various other clock signals are derived. This oscillator is typically a VCO inside a clock generator device, or an external VCO within a clock generator circuit. symbol: The smallest unit of coded data on the medium.