JEDEC JESD203-2005 Standard Test Loads For Dual - Supply Level Translation Devices《双重补给电平转换设备的标准负荷测试》.pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD203NOVEMBER 2005JEDECSTANDARDStandard Test Loads For Dual-Supply Level Translation DevicesNOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approvedthrough the JEDEC Council level and subsequently reviewed and a

2、pproved by the EIA GeneralCounsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and assisting the purchaser in selecting and obtaining

3、 with minimum delaythe proper product for use by those other than JEDEC members, whether the standard is to be usedeither domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption mayinvolve patents or articles, materials, or proces

4、ses. By such action JEDEC does not assume anyliability to any patent owner, nor does it assume any obligation whatever to parties adopting theJEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and applica

5、tion, principally from the solid state device manufacturer viewpoint. No claims to be in conformance with this standard may be made unless all requirements stated in thestandard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publicationshould be addre

6、ssed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard,Arlington, VA 22201-3834, (703)907-7559 or www.jedec.org. Published by JEDEC Solid State Technology Association 2005 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge, however JEDEC re

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8、NT VIOLATE THE LAW! This document is copyrighted by the JEDEC Solid State Technology Association and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid

9、State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 203Page 1STANDARD TEST LOADS FOR DUAL-SUPPLY LEVEL TRANSLATION DEVICES(From JEDEC Board Ballot JCB-05-86, formulated under the cognizance of the JC-40 Committee on Digital Logi

10、c.)1 ScopeThis standard defines ac test loads for dual-supply level translation devices. Uniform test loads enable easy comparison of electrical parameters of dual-supply level translation devices across functions, logic families and IC suppliers.This standard is only intended to apply to devices re

11、leased subsequent to the publication of this document.2 Test setupFigure 1 shows the test setup for measurement of AC parameters. The DUT represents the dual-supply level translation device. VDDIis the supply voltage associated with the input port and VDDOis the supply voltage associated with the ou

12、tput port.NOTE The test fixture design should follow high speed digital design practices appropriate for the waveforms being measured. The goal is to minimize the effect of the test environment on the measured resultsFigure 1 Test setupJEDEC Standard No. 203Page 22 Test setup (contd)2.1 Input signal

13、 characteristicsThe amplitude of the input signal to the DUT can range from 0 to VDDI. The transition time of the input signal should not exceed the value shown in Table 1 for the respective VDDIvalues.Table 1 Input voltage levels for different supply voltagesNOTE Input edge-rates trand tfare measur

14、ed from 10% to 90% of the input signal.2.2 Values of CLand RLfor Different Supply Voltage NodesA load of RL=2k and CL=15pF is used for VDDOvalues of 1.1 V to 5.5 V as shown in Table 2.VDDIMaximum VItror tf1.1 to 1.3 VVDDI 2ns1.4 to 1.6 VVDDI 2ns1.65 to 1.95 VVDDI 2ns2.3 to 2.7 VVDDI 2ns2.7 VVDDI2.5n

15、s3.0 to 3.6 VVDDI2.5ns4.5 to 5.5 VVDDI 6nsTable 2 Capacitive and resistive loads for different VDDO valuesVDDOCLRL1.1 to 1.3 V 15 pF 2k1.4 to 1.6 V 15 pF 2k1.65 to 1.95 V 15 pF 2k2.3 to 2.7 V 15 pF 2k2.7 V 15 pF 2k3.0 to 3.6 V 15 pF 2k4.5 to 5.5 V 15 pF 2kJEDEC Standard No. 203Page 33 Test waveforms

16、 and measurement pointsFigure 2 Test waveformsTable 3 Test measurement points for inputsVDDIMeasurement Point For Inputs1.1 to 1.3 VVDDI/21.4 to 1.6 VVDDI/21.65 to 1.95 VVDDI/22.3 to 2.7 VVDDI/22.7 VVDDI/23 to 3.6 VVDDI/24.5 to 5.5 V VDDI/2aa. For TTL devices, the measurement point is 1.5 VtPLHtPHLV

17、DDI/2VDDO/2VDDI/2VDDO/2INPUTOUTPUTVLOAD= OpenVDDI0 VVOHVOLMEASUREMENT 1. PROPAGATION DELAY TIMEStPZLtPLZVDDI/2VDDO/2VDDI/2VOL+ VOUTPUTCONTROLOUTPUTWAVEFORM 1VLOADAT 2 X VDDOtPHZVDDO/2tPZHVOH-VMEASUREMENT 2. ENABLE AND DISABLE TIMESVDDO/2 VDDO/2tWMEASUREMENT 3. PULSE DURATION (WIDTH)MEASUREMENTSVDDI/

18、2VDDI/2 VDDI/2tSUTIMING INPUTDATA INPUTtHVDDI0 VVDDI0 VMEASUREMENT 4. SETUP AND HOLD TIMESOUTPUTWAVEFORM 2VLOADAT GNDINPUTJEDEC Standard No. 203Page 43 Test waveforms and measurement points (contd)Table 4 Test measurement points for outputsVDDOMeasurement Point For OutputsV1.1 to 1.3 VVDDO/20.1 V1.4

19、 to 1.6 VVDDO/20.1 V1.65 to 1.95 VVDDO/20.15 V2.3 to 2.7 VVDDO/20.15 V2.7 VVDDO/20.3 V3 to 3.6 VVDDO/20.3 V4.5 to 5.5 V VDDO/2aa. For TTL devices, the measurement point is 1.5 V0.3 VRev. 9/02Standard Improvement Form JEDEC JESD82-17The purpose of this form is to provide the Technical Committees of J

20、EDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collected and dispersed to the appropriate committee(s).If you can provide input, please complete this form (it can be edited in Acrobat E

21、xchange) and return to:JEDECAttn: Publications Department2500 Wilson Blvd. Suite 220Arlington, VA 22201-3834Fax: 703.907.75831. I recommend changes to the following: Requirement, paragraph numberTest method number Paragraph numberThe referenced paragraph number has proven to be:Unclear Too Rigid In ErrorOther 2. Recommendations for correction:3. Other suggestions for document improvement:Submitted byName: Phone:Company: E-mail:Address: City/State/Zip: Date: