JEDEC JESD18-A-1993 Standard for Description of Fast CMOS TTL Compatible Logic《快速CMOS TTL兼容逻辑的描述规范》.pdf

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1、- m 3234600 050474B 9TL m EIA JESDLB-A 93 ENGINEERING DOCUMENTS mth lho Penniuion of EIA Undr Rwab Agmnenl Q - JEDEC - STANDARD Standard for Description of Fast CMOS TTL Compatible Logic JESDl8-A (Revision of JEDEC Standard No. 18) JANUARY 1993 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMEN

2、T - II _. _ _ -_I I_ -_I _-_ EIA JESDLB-A 93 3234600 0504749 838 W NOTICE JEDEC Standards and Publications contain material that has been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. JEDEC Standards

3、and Publications are designed to sem the public interest through eliminating misunderstandings between manufacturers and purchases, facilitating interchangeability and improvement of products, and assisting the purchaser is selecting and obtaining with minimum delay the proper product for his partic

4、ular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members, whether the stand

5、ard is to be used either domestically or internationally. JEDEC Standards and Publications are adopted without regard to whether their adoption may involve patents or articles, materials, or processes. By such action, JEDEC does not assume any liability to any patent owner, nor does it assume any ob

6、ligation whatever to parties adopting the JEDEC Standards or Publications. The information included in JEDEC Standards and Publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization

7、there are procedures whereby a JEDEC Standard or Publication may be further processed and ultimately became an EIA Standard. Inquiries, comments, and suggestions relative to the content of this JEDEC Standard should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2001 Pennsylvania

8、 Ave., N.W., Washington, D.C. 2ooo6. Published by ELECTRONIC INDUSTRIES ASSOCIATION Engineering Department 2001 Pennsylvania Ave., N.W. Washington, D.C. 2W6 PRICE: Please refer to the current Catalog of EIA ail otbetinputs at Vcc or Gnd. NOTE3:satscctim6 in Table 1 - 4. uescent + IInputs + IDynamic

9、- NOTE 4: E IC - kC + dIcC NT + QCCD ( fCfl+ fi Ni QuiCscent- Power Supply Current for a TIZ High Input (VI = 3.4 V) Duty cycle forcicii TIZ Input High NUmkrOfTILInpitSatDH Dyaamic charge moved by sn hpui Puise ( HLH or LHL) Qock Fnqwricy fcx cbcked Devices ( Zen, for nonClocked Devices ) uiput Frcq

10、ueacy ofthe i-th input Number afhputo at fi UNIT mA mA mN MHZ mA PF - _-_- - _ _II - EIA JESDLB-A 93 = 3234600 0504757 904 = Pulse Generator JEDEC Standard NO. 18-A Page 6 2. SWITCHING WAVEFORMS FOR 54/74FCTXXX trem I - 3 v PRESET -,I I I I I I SYNCHRONOUS CONTROL PRESET -.3 v CLEAR CLOCK ENABL -e13

11、 v ETC. 1 ov -_ I Its, L 4 I I Lth d I I t I I I I Figure.2-4 Set-up, Hdd and Removal Time Waveforms EIA JESDL-A 93 3234600 05047b0 4T9 = JEDEC Standard NO. 18-A Page 9 ENABLE TIMES Control Input Output Normally Low il 1.5 V I -= Output Normally 1- -,-,-. 1.5 V High DISABLE TIMES Control Input Outpu

12、t Normally Low Output Normally High u ov Figre2-5 Enable and Disable Tie Wavefom JEDEC Standard NO. 18-A Page 10 3, OUTPUT DRIVE FOR 54/74FCTXXX AND 54/74FCTXXXT NUMBER 138 138A 139 139A 161 161A 163 161A 182 1824 191 191A 193 193A 240 240A 241 241A 244 244A 245 USA 273 273A 299 2WA 373 373A 374 374

13、A 377 377A 52 1 521A 533 533A 534 534A TYPE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 The scope of this section shall be to establish output drive categories for the device types listed herein: FYTIXXX FCTXXXT DEVIC bH IOL 0UmJ-r I OH OUTPUT IOL OUTPUT TYPE TYPE TYP

14、E 3 3 3 3 3 3 3 3 3 3 3 3 3 3 6 6 6 6 6 6 6 6 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 3 3 3 3 3 3 6 6 6 6 6 6 6 6 6 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 EIA JESDL-A 93 W 3234600 0504762 271 JEDEC Standard NO. 18-A Page 11 F

15、CTXXXT O DEVICE NUMBER 540 540A 541 541A 563 563A 564 564A 573 513A 574 574A 620 62QA 623 623A 640 64OA 643 643A 645 645A 646 646A 648 648A 821 821A 821B 822 822A 822B 823 823A 823B 824 824A 824B 825 825A 825B 826 826A 826B roL OUTPUT TYPE IOH TYPE IOL OUTPUT TYPE 1 3 1 3 1 1 1 1 1 1 2 2 2 2 2 2 2 2

16、 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 DEVICE NUMBER 827 827A 827B 828 828A 828B 833 841 841A 841B 842 842A 842B 843 843A 843B 844 844A 844B 845 845A 845B 846 846A 846B 853 855 861 81A 86lB 862 86% 862B 863 863A 863B 864 864A 864B _-_-_.I EIA JESDLB-A 93 W 3234600 05047b3 LOB W FCTXXX 2 3

17、2 5 2 5 2 3 2 5 2 5 2 3 2 3 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 5 5 3 5 5 3 5 5 3 5 5 JEDEC Standard NO. 18-A Page 12 F_cTxxxT IOH OUTPUT TYPE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 IOL OUTPUT TYPE 3 5 5 3 3 5 3 3 5 5 5 5 3 5 5 3 5 5 3 5 5 3 5 5 3 3 3 5 5 3 5 5 3 5 5 3

18、 5 5 - EIA JESDLB-A 93 3234600 0504764 044 W JEDEC Standard NO. 18-A Page 13 4. NONSTANDARD DEVICE SPECIFICATIONS 4.1 Scope The scope of this section sha be to describe specifications of individual devices that either are not covered by the main standard or are special exceptions to this standard du

19、e to considerations of device function, design oc appiication. 4.2 Nonstandard Devices _ _I EIA JESDL-A 93 3234600 05047b5 TO = JEDEC Standard NO. 18-A Page 14 5, SWITCHING SPEED STANDARDS FOR 54/74FCTXXX AND 54/74FCTXXXT 5.1 Scope The scope of this section shall be to establish standard hits for sw

20、itching parameters for the FCTXXX and FCTXXXT device types listed herein. For test methodology refer to the waveforms and load circuits d&be in Section 2. 5.2 Form of Device Tables Standardized tirnits for ail switching parameten (dynamic characteristics) are specified by part identifier in numeaica

21、l der within a group. hvic-e types are grouped by generic functional type in Tables 5 - 1 through 5 - 14. Ail hits are in nanoseconds (ns). Generic pin names are used in the tables. No distinction is made for inverting or non-inverting outputs in thenamesunlessnoted. Each table of specifications far

22、 a device type contains the foliowing columns: The first column shows the parameter symbol, The second column shows the corresponding parameter description and minimum or maximum d=b-. The remaining columns show the COMML (74) and MIL (54) limits for each applicable speed &rsde. “he speed grades an

23、identified at the top. As an example, -/T indicates the standard speed grade for 75/54X“XXX and 74/54FcTXXXC NAT indicates the A speed &rade and so on. A dash (-) is inserted whenever a parameter is not specified or does not exist for a given device or speed grade. 5.3 Index of Device Type Tables TA

24、BLE 5 - 1: Gates and Simple BuffeWXnverters TABLE 5 - 2 Bus Drivers, Buffers and Transceivers TABLE 5 - 3: Flipflops and Registers TABU 5 - 4: Latches TABLE 5 - 5 Encodersa Decoders TABLE 5 - 6 Digital Multiplexersand DataSeleCtois TABLE 5 - 7: Amlag Switchts & Muitiplexers/Demultiplexers TABLE 5 -

25、8 COunters TABLE 5 - 9: Synhronous Conters TABU 5 - 10: Shift Registers TABLE 5 - 11: Multivibrators and One-shots TABLE 5 - 12 Cmmtors TABLE 5 - 13: Parity Gem, checkers and Wty Encoders EIA JESDLB-A 93 W 3234600 0504766 917 TABLE 5 - 14 ALUS, Adders and Companion Devices 5.4 Device Type Tables TAB

26、LE 5 - 1: Gates and Shpk Bff-verters “E TABU 5 - 2 Bus Drivers, Buffers and Transceivers JEDEC Standard NO. 18-A Page 15 FCT240 SYMBOL PLH* PHL An-Yn G-O G-O PARAh4ETER DisabbDclay FCT244 FCT245 FCT640 JEDEC Standard NO. 18-A Page 16 FCT645 FCT827 FCT828 EIA JESDLB-A 93 m 3234600 0504768 79T m EDEC

27、Standard NO. 18-A Page 17 FCT863 FCT864 FCT833 - I EIA JESDLB-A 93 = 323qbOO 050q769 b2b EDEC Standard NO. 18-A Page 18 FCT853 SYMBOL PARAMETER /r NAT B/BT C/CT 74 54 74 54 74 54 74 54 tp,tp Maximumlropagation 15.0 18.0 - R-T, T-R &lay PLH,HL hhXhUmOn 19.0 23.0 - R-PAR Delay PHL MaximumprOPegatin 15

28、.0 18.0 - CK,EN-ERR Delay PLH Maximumnopegation 20.0 23.0 - CLR-m Delay tp,tp MaximumRopgation 29.0 33.0 - T, PAR -ERR Dclay, PASS MODE &LH,m MaXhUmhOtiOn 22.0 25.0 - OER-PAR Delay tSU Minimum SearpTime 18.0 21.0 - TQAR-SKm TQAR-CK&b CLR-CK Ti th Minimum Hold Time 0.0 2.0 - QEM Minimum Removal tPZL,

29、tPZH MumOUtPUt 15.0 18.0 - PLZItPHz Mumfitput 15.0 18.0 - G-O Enable Delay G-O Disable Delay FCTS55 - - - - EIA JESDLB-A 93 m 3234600 0504770 348 m JEDEC Standard NO. 18-A Page 19 TABLE 5-3: Switching Parameters for Flip-Fiops FCT273 FCT374 FCT377 - EIA JESDLB-A 73 W 3234600 0504771 284 W EDEC Stand

30、ard NO. 18-A Page 20 FCT534 tPZH,tPZL mmhWt 12.5 14.0 6.5 7.5 5.5 6.2 G - O Enable Delay tPHZ,tPLZ -umOutput 8.0 8.0 5.5 6.5 5.0 5.7 G - O Disable &lay tW Minimum Pluse 7.0 7.0 5.0 6.0 5.0 6.0 CK Dination FCT574 FCT821 tw = Minimum PluSc 7.0 11.0 7.0 7.0 6.0 6.0 6.0 6.0 CK Dmtial tPZH,tPZL mm()UW 12

31、.0 14.0 12.0 14.0 8.0 9.0 7.0 8.0 G - O EiiableDelay PHZ,PLZ tPUt 12.0 14.0 12.0 14.0 8.0 8.0 6.2 6.2 G - O Disable Delay EIA JESDLB-A 73 = 3234600 0504772 110 - _ EIA JESDLB-A 73 m 3234600 0504773 057 m JEDEC Standard NO, 18-A Page 22 FCT824 h Minimum Hold Time 2.0 3.0 2.0 2.0 1.5 1.5 1.5 1.5 trem

32、Minimum Removal 7.0 7.0 7.0 7.0 6.0 6.0 6.0 6.0 tSU Minimum Setup Time 4.0 6.0 4.0 4.0 3.0 3.0 3.0 3.0 h Minimum Hold Time 2.0 3.0 2.0 3.0 0.0 0.0 0.0 0.0 tw Minimum Pluse 7.0 11.0 7.0 7.0 6.0 6.0 6.0 6.0 CK Duratiai tw Minimum Pluse 7.0 11.0 7.0 7.0 6.0 6.0 6.0 6.0 cLR* Duratial kZH,W WmhQUt 12.0 1

33、4.0 12.0 14.0 8.0 9.0 7.0 8.0 G - O Enable Delay tPHZ,tPLZ -umQJtput 12.0 14.0 12.0 14.0 8.0 8.0 6.5 6.5 G - O DisableDelay CK - D CLR*-CK Time CE* -a CK - CE* FCT825 SYMBOL PARAMETER NAT B/BT C/CT CK - Q Delay CLR - Q Delay 74 54 74 54 74 54 74 54 QLH, Maximum propagation 12.0 14.0 10.0 11.5 7.5 8.

34、5 6.0 7.0 tp,tpm Maximumpropegation 14.0 15.0 14.0 15.0 9.0 9.5 8.0 8.5 tSU Minimum Setup Time 4.0 6.0 4.0 4.0 3.0 3.0 3.0 3.0 th Minimum Hold Time 2.0 3.0 2.0 2.0 1.5 1.5 1.5 1.5 trem Minimum Removal 7.0 7.0 7.0 7.0 6.0 6.0 6,O 6,O tSU Minimum SearpTune 4.0 6.0 4.0 4.0 3.0 3.0 3.0 3.0 th :iirullmum

35、HddTimc 2.0 3.0 2.0 3.0 0.0 0.0 0.0 0.0 tw Minimum Pluse 7.0 11.0 7.0 7.0 6.0 6.0 6.0 6.0 CK Drsation . tw Minimum Pluse 7.0 11.0 7.0 7.0 6.0 6.0 6.0 6.0 cLR* Dirratiai tPZH,tPZL WmhqHlt 12.0 14.0 12.0 14.0 8.0 9.0 7.0 8.0 G - O Enable Delay tpHZ,tpLZ -umOutput 12.0 14.0 12.0 14.0 8.0 8.0 6.5 6.5 G

36、- O DisableDelav D - CK CK - D cLR*-cK Tim CE* -cK CK - CE* . ELA JESDLB-A 93 m 3234600 0504774 793 W JEDEC Standard NO. 18-A Page 23 FCT826 TABLE 5 -4 Switchingprirameters for Latches FCT373 - - - - - - - - EIA JESDLB-A 93 3234600 0504775 92T th E - D tW E tPZH,tPZL G - O Q“Z.PLZ G - O Minimum Hold

37、 Time 3.0 3.0 1.8 2.0 - 1.5 1.5 Minimumpulse 6.0 6.0 5.0 6.0 5.0 6.0 Durarim MmhW 12.0 13.5 8.0 9.5 5.5 6.3 EnableDelay Maximum hW 7.5 10.0 5.8 6.5 5.0 5.9 DisableDelay I PHZ,PLZ MuhW G -O I Disahle Delav I 12.0 I 14.0 I 12.0 I 14.0 I 7.0 I 7.5 I 6.0 I 6.3 I i EIA JESDLB-A 93 m 3234600 0504776 bb m

38、JEDEC Standard NO. 18-A Page 25 FCT844 SYMBOL PLH, PHL PLH, PHL D - Q E - Q bu D - E th E - D PLHs QHL R,S - Q trem RIS - Q tsU S - E tBU R - E tW R,S tPZH,tPZL G - O PHZ.PLZ G - O - _I - - _ _- EIA JESDLB-A 73 m 3234600 0504777 7T2 m JEDEC Standard NO. 18-A Page 26 PARAMETER /r NAT B/BT C/CT Maximu

39、m Propagation 11.0 I 14.0 9.5 I 11.0 6.5 I 7.5 5.5 I 6.3 74 I 54 74 I 54 74 I 54 74 I 54 _ Delay Maximumpropagatioa 12.0 14.0 12.0 13.0 8.0 10.5 6.4 6.8 b Delay Minimum Setup Tie 3.0 3.0 2.5 2.5 2.5 2.5 2.5 2.5 Minimum HOM Time 4.0 4.0 25 3.0 2.5 2.5 2.5 2.5 Maximumnapagation 13.0 15.0 12.0 14.0 8.0

40、 10.0 7.0 9.0 I I I I I I I I Minimum Removal I 13.0 I 15.0 I 12.0 I 14.0 I 8.0 I 10.0 I 7.0 I 9.0 ri Minimum Setup Time 4.0 4.0 4.0 4.0 3.0 3.0 2.5 2.5 Minimum Setup Time 3.0 3.0 3.0 3.0 2.5 2.5 2.5 2.5 I I I 1 Minimumpulse I 8.0 I 12.0 I 8.0 I 9.0 I 4.0 I 4.0 I 4.0 I 4.0 1 Diaatiai Maximumoutput 12.0 14.0 12.0 14.0 8.0 8.5 6.5 7.3 Enabkhlay Maximum aumt 12.0 14.0 12.0 14.0 7.0 7.5 6.0 6.3 Disable Delay I I I I I I I I I FCT84S