JEDEC JESD12-1985 Standard for Gate Array Benchmark Set《门阵列基准电设置标准》.pdf

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1、EIA JESDL2 85 3234600 0004777 b ,Y. - JEDECSTANDARD No. 12 STANDARD - FOR. GATEARRAY BENCHMARK SET JEDEC Solid state Products Engineering Counul I EIA JESDL2 85 m 3234b00 0004778 8 m NOTICE EDEC Standards and Publications contain material that has been prepared, progressively reviewed, and approved

2、through the JEDEC Cwncil level and subsequently reviewed and approved by the EIA General Counsel. JEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating inter- changeability and improvement o

3、f products, and assisting the purchaser in selecting and obtainng with minimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling products not conforming to such standards, nor

4、 shall the existence of such standards preclude their voluntary use by those other than EIA members whether the standard is to be used either domestically or internationally. Recommended Standards and Publications are adopted by JEDEC without regard to whether or not their adoption may involve paten

5、ts or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC Standards or Publications. The information included in JEDEC Standards and Publications represents a sound approac

6、h to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC Standard or Publication may be further processed and ultimately become an EIA Standard. . Inquiries, comments, and suggestion

7、s relative to the content of this JEDEC Standard or Publication should be addressed .to the JEDEC Executive Secretary at EIA Headquarters, 2001 Eye Street, N.W., Washington, D.C. 20006. I Published by ELECTRONIC INDUSTRIES ASSOCIATION Engineering Department 2001 Eye Street, N.W. Washington, D.C. 200

8、06 Copyright 1985 ELECTRONIC INDUSTRIES ASSOCIATION PRICE: $8.00 Printed in U.S.A. JEDEC Standard No. 12 e STANDARD FOR GATE ARRAY BENCHMARK SET . TABLE OF CONTENTS Paraqraph 1.0 PURPOSE 2.0 REASON FOR REQUIREMENT 3.0 VENDOR PRESENTATION OF DATA 3.1 Performance Data 3.2 Performance Results Paqe 1 1

9、1 1 1 3.3 Specified Parameters 2 BENCHMARK 1 - 4 Bit ALU BENCHMARK 2 - 16 Bit ALU BENCHMARK 3 - 4 Bit Rotator BENCHMARK 4 - 16 Bit Rotator BENCHMARK 5 - 8 Bit Register BENCHMARK 6 - 8 Up/Down Counter BENCHMARK 7 - 3 to 8 Decoder BENCHMARK 8 - 16 x 4 RAM 10 BENCHMARK 9 - 9 Bit Parity Generator 11 4 *

10、 EIA JESDLZ 85 3234600 0004780 b JEDEC Standard No. 12 Page 1 STANDARD FOR GATE ARRAY BENCHMARK SET (From JEDEC Council Ballot JCB-83-29, formulated under the cognizance of JC-44 Committee on Gate Arrays.) 1.0 PURPOSE The purpose of these benchmarks is to provide a common set of high level functions

11、 which serve as vehicles for comparing the performance of gate arrays implemented in any technology using any internal structure. These benchmarks effectively provide an unbiased measure of gate array vendors ability to implement a desired complex function on a particular gate array at a known level

12、 of performance 2.0 REASON FOR REQUIREMENT Users of gate array technology encounter a great deal of difficulty in coming up with estimates of realistic performance measures for potential designs. This is because most performance data currently specified by industry vendors exists at SCI level (viz N

13、AND, NOR, INVERTER). Users need to know in advance of beginning a design, the estimated performance of some commonly used MSI functions such as counters, decoders, octal flip-flops, small ALUS etc. From this data they are able to construct an estimate of performance of critical portions of their res

14、pective designs and check the feasibility of building that circuit using a specified gate array technology. 3.0 VENDOR PRESENTATION OF DATA e While it is by no means mandatory that gate array vendors provide this data, a JEDEC standard benchmark inherently provides more consistency and structure in

15、the gate array marketplace which is advantageous to both vendors and users. 3.1 Performance Data Vendors may choose to provide their customers with such performance data based purely on simulated designs or alternatively choose to implement such macro elements as portions of test chips which they ma

16、y make available to customers for evaluation. 3.2 Performance Results . In all cases these performance results and parameters must specify the con- ditions and methods under which they are derived. include not only all they array elements that are used to implement the function, but also those that

17、have been made inaccessible or unusable due to routing constraints. Wherever multiple ac paths are possible from an input to an output, the vendor will specify the longest path. Array utilization should EIA JESDLZ! 85 m 3234600 0004781 8 m JEDEC Standard No. 12 Page 2 3.3 Specified Parameters Parame

18、ters specified should include but are not limited to: (1) (2) (3) DC static power, Total array elements used to implement each logic macro. Worst case dynamic power at vendor specified frequencies. I / EIA JESDL2 85 3234600 0004782 T JEDEC Standard No. 12 Page 3 Carry Propagate Carry Generate Carry

19、Out Result Result Result Result The ALU must implement at least the following set of functions: O ADD A+B+C SUB A- B+C RSB B- A+C AND A&B OR A!B XOR A XOR 6 The specified performance parameters are: Max Delay - - . Max Delay Max Delay Max Delay Max Delay Max Delay Max Delay . Max Delay Max Delay Max

20、 Delay Max Delay Max Delay Max Delay Max Delay Any A to Any F Any A to P Any A to G Any A to Cout Any B to Any F Any B to P Any B to G . Any B to Cout AhyS to Any F Any C to P Any S to G Any S to Cout Cin to Any F Cin to Cout Total Gates or Celis used. EIA JESDL2 85 m 3234600 0004783 L m JEDEC Stand

21、ard No. 12 Page 4 BENCHMARK 2 16 Bit ALU, similar to 74S381 - Data in A15 - I lo - P/L Carry Propagate h -* I lo - G/L Carry Generate v -3 I I - Cout Carry Out AO -j I Data in 615 -I h -I .v -I I Select SZ - 1 I s1 -I I so -I I Carry in Gin-/ _ I BO -I Result Result Result Result The ALU must implem

22、ent at least the following set of functions: ADD SUB RSB AND OR XOR A+B+C A- B+C 6- A+C A&B A! B A XORB The specified performance parameters are: .Max Delay Max Delay Max Delay Max Delay Max Delay Max Delay Max Delay Max Delay Max Delay Max Delay Max Delay Max Delay Max Delay Max Delay Any A to Any

23、F Any A to P Any A to G Any A to Cout Any B to Any F Any B to P Any B to G Any B to Cout Any S to Any F Any S to P Any S to G Any S to Cour Cin to Any F Cin to Cout I Total Gates or Cells used. JEDEC Standard No. 12 Page 5 BENCHMARK 3 4 Bit Rotator 1 - I Data in 03 -I I - F3 D2 -I I - F2 D1 -I DO -I

24、 I Select Si -I so -I -_- Result Result The rotater implements the followings functions: Function S1 SO F3 F2 F1 FO PASS O O 03 02 D1 DO ROT1 O 1 D2 D1 DO D3 O ROT2 1 O D1 DO D3 D2 ROT3 i 1 DO D3 D2 D1 The specified performance parameters are: Max Delay Max Delay Any D to Any F Any S to Any F . Tota

25、l Gates or Cells used. EIA JESDLE! 85 3234600 0004785 5 E JEDEC Standard No. 12 Page 6 BENCHMARK 4 16 Bit Rotator The effic,mcy a a topologically complex function which will generally require a lot of metal. large &,.ifter .and multiplexor type func-ions. Also presen-c routers w Result Result Result

26、 Result The rotator implements the following functions: The specified performance parameters are: Max Delay Max Delay Any S to Any F Any S to Any F Total Gates or Cells used. h f EIA JESD12 85 m 3234600 0004786 7 m JEDEC Standard No. 12 Page 7 BENCHMARK 5 8 Bit Register, similar to 74S374 Test flip

27、flop performance. - I I Data Result Result Result Result Result Result Result QO Result DO -I I - The specified performance parameters are: Min Setup at Any D to Clock 4 Min Hold for Any D after Clock Max Delay Clock kto any Q Total Gates or Cells used. EIA JESDLZ 85 m 3234b00 0004787 9 m JEDEC Stan

28、dard No. 12 Page 8 BENCHMARK 6 8 Up/Down Counter Test counter performance. - 1 I Data in D7 -I 1 - Q7 D6 -I I - Q6 D5 -I 1 - Q5 04 -I I - Q4 D3 -I I - Q3 02 -I I - Q2 D1 -I I - Q1 DO -I 1 - QO I I s1 -I I -I - -, 2 “-I so I Clock -_- + Minimum functions: Result Result Result Result Result Result Res

29、ult Result s1 so Function O O NOP Outputs Unchanged O 1 Load Q (7 : O := D after Clock i 1 O INC Q 7 : O := Q + 1 after Clock4 1 3 DEC Q 7 : O := Q c 7 : O - 1 after Clock The specified performance parameters are: Min Setup at Any D to Clock 4 Min Hold for Any D after Clock 4 Min Setup at Any S to C

30、lock 4 Min Hold for Any S after Clock 4 Max Delay Clock 4 to any Q, Load mode Max Delay Clock 4 to any Q, INC mode Max Delay Clock4 to any Q, DEC mode Maximum guaranteed count frequency. Total Gates. or Cells used. - r cr EIA JESDLZ 85 I 3234600 0004788 O I JEDEC Standard No. 12 Page 9 BENCHMARK 7 3

31、 to 8 Decoder, similar to 74S138 Test decoder and control logic capabilities. - I I GZ/L o I I ENABLES Gl/L O I 1 GO -+ I I I I O - 07/L I I O - 06/L I I O - 05/L I I O - 04/L I i O - 03/L 1 I o -a 02/L I I o - 01/L I 1 o - OO/L SELECT S2 - I I I I - Minimum function: ENABLES SELECT G2 Gl GO s2 s1 s

32、o H XX xxx X HX xxx x XL xxx L LH LLL L LH LLH L LH LHL L LH LHH L LH HtL L LH HLH L LH HHL L LH HHH The specified performance parameters are: OUTPUTS OUTPUTS 07 06 05 04 03 O2 O1 O0 H HH HH H H H H HHHH H H H H HH HH H H H H HH HH H H L H HH HH H L H H HH HH L H H H HH HL H HH HHHLH HHH H HL HH H H

33、 H HLHHH HHH L HH HH H H H Max Delay G2 to any O Max Delay G1 to any O Max Delay GO to any O Max Delay S2 to any O Max Delay S1 to any O Max Delay SO to any O Total Gates or Cells used. _ EIA JESDL2 85 W 3234b00 0004789 2 W JEDEC Standard No. 12 Page 10 BENCHMARK 8 16 x 4 RAM, similar to 74C189 Test

34、s cost of memory. - I I DATA IN D3 -I I - Y3 OUTPUT DZ -I I - Y2 Dl - ADDRESS A3 - A2 - Al - AO -I I I I WRITE WE/L - o I I SELECT CS/L- O I I OUTPUT OE/L-O I _ 1 ENABLE The specified performance parameters are: Max Delay Any A to Any Y Max Delay CS to Any Y Max Delay OE to Any Y Min Setup CS before

35、 WE low Min Setup A before WE low Min Hold A after WE rising edge Min Setup D before WE rising edge Min Hold D after WE rising edge Min Write pulse width. Total Gates or Cells used. I - Y1 I - YO I I I I - . . -1 i. - EIA JESDL2 85 W 3234b00 0004770 9 W _ - JEDEC Standard No. 12 Page 11 BENCHMARK 9

36、9 Bit Parity Generator, similar to 74S280 - . I8 - I I I7 - I I I6 - I I I 0 - I - I .I2 - I I1 - I I I 10 - I. I5 - I INPUT I4 - I I OUTPUT 2 ODD I3 - I - FUNCTION EVEN True if the sum of I8 to IO is even. ODD True if the sum of I8 to IO is odd. Performance Parameters: Max Delay Max Delay Any I to EVEN Any I to ODD O Total Gates or Cells used.