JEDEC JESD11-1984 Chip Carrier Pinouts Standardized for CMOS 4000 HC and HCT Series of Logic Circuits《CMOS 4000、HC以及逻辑电路的HCT系列片状载体插脚引线标准化》.pdf

《JEDEC JESD11-1984 Chip Carrier Pinouts Standardized for CMOS 4000 HC and HCT Series of Logic Circuits《CMOS 4000、HC以及逻辑电路的HCT系列片状载体插脚引线标准化》.pdf》由会员分享，可在线阅读，更多相关《JEDEC JESD11-1984 Chip Carrier Pinouts Standardized for CMOS 4000 HC and HCT Series of Logic Circuits《CMOS 4000、HC以及逻辑电路的HCT系列片状载体插脚引线标准化》.pdf（10页珍藏版）》请在麦多课文档分享上搜索。

1、A ui EIA JESDLL 84 W 3234600 O004767 3 W DECEMBER 1984 JEDEC STANDARD No. 11 CHIP CARRIER PINOUTS STANDARDIZED FOR CMOS 4000, HC AND HCT SERIES OF LOGIC CIRCUITS JEDEC Solid State Products Engineering Council EIA JESDLL 84 m 3234600 O004768 5 m NOTICE This JEDEC Standard/Publication contains materia

2、l which has been prepared and progressively reviewed and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. JEDEC Standards/Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and

3、purchasers, facili- tating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or non-member of JEDEC from manufa

4、cturing or selling products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members whether the standard is to be used either domestically or internationally. JEDEC Standards and Publications are adopted by JEDEC withou

5、t regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC Standards or Publications. The information included in

6、JEDEC Standards/Publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC Standard/Publication may be further processed and ultimately become an

7、 EIA Standard. Inquiries, comments, and suggestions relative to the content of this JEDEC Standard/Publication should be addressed to the JEDEC Executive Secretary at the EIA Headquarters. JEDEC Electronic Industries Association 2001 Eye Street N.W. Washington, D.C. 20006 Published by ELECTRONIC IND

8、USTRIES ASSOCIATION Engineering Department 2001 Eye Street, N.W. Washington, D.C. 20006 PRICE: $6.00 Printed in U.S.A. * a EIA JESDLL 84 m 3234600 00047b 7 m JEDEC Standard No. 11 CHIP CARRIER PINOUTS STANDARDIZED FOR CMOS 4000, HC AND HCT SERIES OF LOGIC CIRCUITS O NOTE TO THE READER Numbering of J

9、EDEC Standard follows a numerical sequence which does not necessarily relate to the publication date of the document. -1- t a EIA JESDLL 84 m 3234600 0004770 3 m JEDEC Standard No. 11 Page 1 e CHIP CARRIER PINOUTS STANDARDIZED FOR CMOS 4000, HC AND HCT SERIES OF LOGIC CIRCUITS (From JEDEC Council Ba

10、llot JCB-82-26A, formulated under the cognizance of JC-40.2 Committee on CMOS Integrated Logic Devices.) 1.0 INTROOUCTION The following criteria shall be used to convert existing DIP and Flat Package SSI, MSI pinouts for digital parts to chip carrier packages: A. Chip carrier packages to be used sha

11、ll be either the: (1) (2) 20-lead, ,350 inch x .350 inch, Type C package, or the 28-lead, .450 inch x .450 inch, Type C package. B. Device conversion shall be as follows: DIP PACKAGE CHIP CARRIER PACKAGE FLAT PACKAGE OR 14 - Lead 20 - Lead 16 - Lead 18 - Lead 20 - Lead 24 - Lead . 28 - Lead 28 - Lea

12、d EIA JESDLL 84 m 3234600 0004773 5 m 1 JEDEC Standard No. 11 Page 2 c. D. E. The pinout conversians shall be in accordance with the diagrams shown in Figures 1 - 4. Each device shall be pinned out based on its present package/pinout and the Conversion Table I shown on page 3. Devices presently in 2

13、0 and 28-Lead packages shall be pinnedout 1:l in in chip carriers. Bias voltages for chip carriers will be designated by the following standard convention: The most positive bias voltage required by the device shall be assigned to the highest numbered terminal. The most negative bias voltage require

14、d by the device shall be assigned to the terminal number that is half the highest terminal number. Other required bias voltages shall be assigned terminal numbers in accordance with the appropriate mapping figure, referenced under paragraph C. When this convention conflicts with the mapping guidelin

15、es as shown in the paragraph above, this convention will take precedence. The remaining connections will then be assigned in sequence leaving the same “No connect“ terminals as indicated in the Figures referenced in paragraph C. ! JEDEC Standard No. 11 Page 3 EIA JESDLL 84 = 3234600 0004773 9 JEDEC

16、Standard No. 11 Page 4 o lel o Lbi NC o o o (TOP VIEW) CHIP-CARRIER TERMINAL NUMBER DUAL-.IN-LINE LEAD NUMBER t FIGURE 1 14 - LEAD PINOUT FOR 20-TERMINAL CHIP CARRIER i EIA JESDLL 84 m 3234600 0004774 O m JEDEC Standard No. 11 Page 5 (TOP VIEW) 0 CHIP-CARRIER TERMINAL NUMBER 0 DUAL-IN-LINE LEAD NUMB

17、ER FIGURE 2 16 - LEAUXNOUT FOR-ZO-TERWTNAL CHIP CARRIER EIA JESDLL 84 3234600 0004775 2 m JEDEC Standard No. 11 Page 6 , El . T;ol NC NC FIGURE 3 18-LEAD PINOUT FOR 20-TERMINAL CHIP CARRIER J- 3. EIA JESDLL 84 = 3234600 000477b 4 JEDEC Standard No. 11 Page 7 (TOP VIEW) CHIP-CARRIER TERMINAL NUMBER DUAL-IN-LINE LEAD NUMBER FIGURE4 24-LEAD PINOUT FOR 28-TERMINAL CHIP CARRIER