ETSI TR 102 580-2007 Terrestrial Trunked Radio (TETRA) Release 2 Designer-s Guide TETRA High-Speed Data (HSD) TETRA Enhanced Data Service (TEDS) (V1 1 1)《陆地集群无线电(TETRA) 第2次发布 设计员指南.pdf
《ETSI TR 102 580-2007 Terrestrial Trunked Radio (TETRA) Release 2 Designer-s Guide TETRA High-Speed Data (HSD) TETRA Enhanced Data Service (TEDS) (V1 1 1)《陆地集群无线电(TETRA) 第2次发布 设计员指南.pdf》由会员分享,可在线阅读,更多相关《ETSI TR 102 580-2007 Terrestrial Trunked Radio (TETRA) Release 2 Designer-s Guide TETRA High-Speed Data (HSD) TETRA Enhanced Data Service (TEDS) (V1 1 1)《陆地集群无线电(TETRA) 第2次发布 设计员指南.pdf(188页珍藏版)》请在麦多课文档分享上搜索。
1、 ETSI TR 102 580 V1.1.1 (2007-10)Technical Report Terrestrial Trunked Radio (TETRA);Release 2;Designers Guide;TETRA High-Speed Data (HSD);TETRA Enhanced Data Service (TEDS)ETSI ETSI TR 102 580 V1.1.1 (2007-10) 2 Reference DTR/TETRA-04178 Keywords data, service ETSI 650 Route des Lucioles F-06921 Sop
2、hia Antipolis Cedex - FRANCE Tel.: +33 4 92 94 42 00 Fax: +33 4 93 65 47 16 Siret N 348 623 562 00017 - NAF 742 C Association but non lucratif enregistre la Sous-Prfecture de Grasse (06) N 7803/88 Important notice Individual copies of the present document can be downloaded from: http:/www.etsi.org T
3、he present document may be made available in more than one electronic version or in print. In any case of existing or perceived difference in contents between such versions, the reference version is the Portable Document Format (PDF). In case of dispute, the reference shall be the printing on ETSI p
4、rinters of the PDF version kept on a specific network drive within ETSI Secretariat. Users of the present document should be aware that the document may be subject to revision or change of status. Information on the current status of this and other ETSI documents is available at http:/portal.etsi.or
5、g/tb/status/status.asp If you find errors in the present document, please send your comment to one of the following services: http:/portal.etsi.org/chaircor/ETSI_support.asp Copyright Notification No part may be reproduced except as authorized by written permission. The copyright and the foregoing r
6、estriction extend to reproduction in all media. European Telecommunications Standards Institute 2007. All rights reserved. DECTTM, PLUGTESTSTM and UMTSTM are Trade Marks of ETSI registered for the benefit of its Members. TIPHONTMand the TIPHON logo are Trade Marks currently being registered by ETSI
7、for the benefit of its Members. 3GPPTM is a Trade Mark of ETSI registered for the benefit of its Members and of the 3GPP Organizational Partners. ETSI ETSI TR 102 580 V1.1.1 (2007-10) 3 Contents Intellectual Property Rights8 Foreword.8 1 Scope 9 2 References 9 2.1 Informative references9 3 Definitio
8、ns and abbreviations.11 3.1 Definitions11 3.2 Abbreviations .16 4 TETRA layered architecture 19 4.1 OSI reference model.19 4.2 TETRA protocol stack21 4.2.1 Protocol architecture.21 4.2.2 Inter-layer communication22 4.2.3 Testable boundaries 22 4.2.4 Service access points 23 5 Overview of TETRA High-
9、Speed Data (HSD)23 5.1 Introduction 23 5.2 Physical layer and lower MAC layer enhancements 24 5.3 Higher protocol layer enhancements 25 5.4 Services and applications .25 6 Physical layer and lower MAC 26 6.1 Physical resources 26 6.2 TDMA frame structure.27 6.3 Slot structure 28 6.3.1 Slot structure
10、 for phase modulation 28 6.3.2 Slot structure for QAM .29 6.4 Radio transmission burst structure .30 6.4.1 Burst structure for phase modulation30 6.4.2 Burst structure for QAM.32 6.4.3 Burst structure formats34 6.4.3.1 Phase modulated burst formats .34 6.4.3.2 QAM modulated burst formats .34 6.5 Cha
11、nnel structure35 6.5.1 Logical channels in phase modulation35 6.5.1.1 Control CHannel (CCH) .35 6.5.1.2 Traffic CHannel (TCH).36 6.5.2 QAM channels 36 6.5.3 Mapping of logical channels into physical channels.37 6.5.3.1 Mapping in phase modulation.37 6.5.3.2 Mapping in QAM37 6.6 Reference configurati
12、on .38 6.6.1 Reference configuration for phase modulation.38 6.6.2 Reference configuration for QAM39 6.7 Modulation .39 6.7.1 Phase modulation39 6.7.2 QAM.41 6.7.2.1 Modulation types.41 6.7.2.2 Bit to symbol mapping41 6.7.2.3 Comparison of gross bit rates45 6.8 Error control (lower MAC) 45 6.8.1 Gen
13、eral45 6.8.2 Error control schemes for phase modulation 47 6.8.3 Error control schemes for QAM channels 48 ETSI ETSI TR 102 580 V1.1.1 (2007-10) 4 6.8.3.1 Slot Information CHannel - QAM/Uplink (SICH-Q/U)49 6.8.3.2 Slot Information CHannel - QAM/Downlink (SICH-Q/D).49 6.8.3.3 Access Assignment CHanne
14、l - QAM (AACH-Q).50 6.8.3.4 Signalling Channel - QAM/Half slot Uplink (SCH-Q/HU) 50 6.8.3.5 Signalling CHannel - QAM/Uplink (SCH-Q/U).51 6.8.3.6 Signalling CHannel - QAM/Downlink (SCH-Q/D) and Broadcast Network CHannel - QAM (BNCH-Q).51 6.8.3.7 Signalling CHannel - QAM/Random Access (SCH-Q/RA)51 6.8
15、.4 Coding for phase modulation52 6.8.4.1 General52 6.8.4.2 16-state Rate-Compatible Punctured Convolutional (RCPC) codes .52 6.8.4.3 Shortened (30,14) Reed-Muller block codes.54 6.8.4.4 Cyclic Redundancy Check (CRC) block code 54 6.8.5 Coding for QAM channels55 6.8.5.1 8-state Parallel Concatenated
16、Convolutional Code (PCCC) for QAM .55 6.8.5.1.1 Encoding by the upper 8-state RSC encoder of rate 1/256 6.8.5.1.2 Interleaving by the quadratic-congruence interleaver57 6.8.5.1.3 Encoding the interleaved bits by the lower 8 state RSC encoder of rate 1/2.58 6.8.5.1.4 Merging the systematic and parity
17、 bits for the PCCC encoder58 6.8.5.1.5 Puncturing scheme for the PCCC encoder 58 6.8.5.1.6 Puncturing mask for the PCCC encoder with coding rate 2/3 .58 6.8.5.1.7 Puncturing mask for the PCCC encoder with coding rate 1/2 .59 6.8.5.2 (16,5) Reed-Muller (RM) code for QAM .59 6.8.6 Interleaving for pha
18、se modulation 59 6.8.7 Interleaving for QAM channels 60 6.8.8 Scrambling60 6.8.8.1 General60 6.8.8.2 Scrambling method .61 6.9 Synchronization and channel estimation 61 6.9.1 Frequency and time synchronization 61 6.9.1.1 Requirements 61 6.9.1.1.1 BS requirements 61 6.9.1.1.2 MS requirements .61 6.9.
19、1.2 Initial synchronization via pi/4-DQPSK plus pi/8-D8PSK .61 6.9.1.3 Synchronization in QAM channels .62 6.9.2 Channel estimation in QAM channels 65 6.10 Power control .66 6.11 Link adaptation in TETRA high speed channels66 7 Higher layer protocol66 7.1 Protocol architecture.66 7.1.1 General packe
20、t data aspects 66 7.1.2 Architecture of the TETRA protocol stack.67 7.2 Multimedia Exchange layer68 7.2.1 General MEX features 68 7.2.2 MEX routing services .68 7.2.3 MEX precedence 69 7.3 Subnetwork Dependent Convergence Protocol layer .69 7.3.1 Outline of SNDCP 69 7.3.2 Application-level QoS param
21、eters72 7.3.3 QoS negotiation 74 7.3.4 QoS filtering information for secondary PDP contexts 74 7.3.5 Assignment of PDP contexts to layer 2 communication links 75 7.3.6 Choice of layer 2 communication link parameters .75 7.3.7 Selection of physical channel76 7.3.7.1 Initial PDCH access 76 7.3.7.2 Cha
22、nging PDCH requirements76 7.3.8 Header and data compression .76 7.3.9 Data priority in SNDCP77 7.3.10 Reconnection following cell reselection.77 7.4 Operation of the data link layer (layer 2) protocol .77 7.4.1 Structure of the data link layer77 ETSI ETSI TR 102 580 V1.1.1 (2007-10) 5 7.4.2 Control
23、channel usage.79 7.4.2.1 Common control channels and assigned channels 79 7.4.2.2 pi/4-DQPSK channel80 7.4.2.3 D8PSK channel .80 7.4.2.4 QAM channel80 7.4.2.5 Slot and TDMA frame arrangement on uplink and downlink.81 7.4.2.6 Minimum mode.82 7.4.2.7 Discontinuous downlink transmissions - time-sharing
24、 mode82 7.4.2.8 Independent allocation of uplink and downlink 82 7.4.3 Communication links provided by the LLC .83 7.4.3.1 General83 7.4.3.2 Basic link 83 7.4.3.3 Advanced link .84 7.4.3.4 Segment size for advanced link.85 7.4.3.5 Layer 2 signalling87 7.4.4 Some MAC processes.87 7.4.4.1 General87 7.
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