ETSI GS SMT 001-2015 Surface Mount Technology (SMT) Requirements for Embedded Communication Modules For Machine To Machine Communications (V2 1 1)《表面焊接技术 (SMT) 机器对机器通信用嵌入式通信模块的要求 (_1.pdf

《ETSI GS SMT 001-2015 Surface Mount Technology (SMT) Requirements for Embedded Communication Modules For Machine To Machine Communications (V2 1 1)《表面焊接技术 (SMT) 机器对机器通信用嵌入式通信模块的要求 (_1.pdf》由会员分享，可在线阅读，更多相关《ETSI GS SMT 001-2015 Surface Mount Technology (SMT) Requirements for Embedded Communication Modules For Machine To Machine Communications (V2 1 1)《表面焊接技术 (SMT) 机器对机器通信用嵌入式通信模块的要求 (_1.pdf（69页珍藏版）》请在麦多课文档分享上搜索。

1、 ETSI GS SMT 001 V2.1.1 (2015-06) Surface Mount Technology (SMT); Requirements for Embedded Communication Modules For Machine To Machine Communications Disclaimer This document has been produced and approved by the Surface Mount Technique (SMT) ETSI Industry Specification Group (ISG) and represents

2、the views of those members who participated in this ISG. It does not necessarily represent the views of the entire ETSI membership. GROUP SPECIFICATION ETSI ETSI GS SMT 001 V2.1.1 (2015-06)2Reference RGS/SMT-002 Keywords communications module, M2M, SMT ETSI 650 Route des Lucioles F-06921 Sophia Anti

3、polis Cedex - FRANCE Tel.: +33 4 92 94 42 00 Fax: +33 4 93 65 47 16 Siret N 348 623 562 00017 - NAF 742 C Association but non lucratif enregistre la Sous-Prfecture de Grasse (06) N 7803/88 Important notice The present document can be downloaded from: http:/www.etsi.org/standards-search The present d

4、ocument may be made available in electronic versions and/or in print. The content of any electronic and/or print versions of the present document shall not be modified without the prior written authorization of ETSI. In case of any existing or perceived difference in contents between such versions a

5、nd/or in print, the only prevailing document is the print of the Portable Document Format (PDF) version kept on a specific network drive within ETSI Secretariat. Users of the present document should be aware that the document may be subject to revision or change of status. Information on the current

6、 status of this and other ETSI documents is available at http:/portal.etsi.org/tb/status/status.asp If you find errors in the present document, please send your comment to one of the following services: https:/portal.etsi.org/People/CommiteeSupportStaff.aspx Copyright Notification No part may be rep

7、roduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm except as authorized by written permission of ETSI. The content of the PDF version shall not be modified without the written authorization of ETSI. The copyright and the foregoing restrict

8、ion extend to reproduction in all media. European Telecommunications Standards Institute 2015. All rights reserved. DECTTM, PLUGTESTSTM, UMTSTMand the ETSI logo are Trade Marks of ETSI registered for the benefit of its Members. 3GPPTM and LTE are Trade Marks of ETSI registered for the benefit of its

9、 Members and of the 3GPP Organizational Partners. GSM and the GSM logo are Trade Marks registered and owned by the GSM Association. ETSI ETSI GS SMT 001 V2.1.1 (2015-06)3Contents Intellectual Property Rights 7g3Foreword . 7g3Modal verbs terminology 7g3Introduction 7g31 Scope 8g32 References 8g32.1 N

10、ormative references . 8g32.2 Informative references 9g33 Definitions and abbreviations . 9g33.1 Definitions 9g33.2 Abbreviations . 10g34 Physical Form Factor Specifications 11g34.0 Physical Form Factor introduction . 11g34.1 SMT Module Layouts 12g34.1.0 SMT Layout Family and Common Properties 12g34.

11、1.1 SMT3136 Module Mechanical Properties 12g34.1.2 SMT3129 Module Mechanical properties 15g34.1.3 SMT3122 Module Mechanical properties 18g34.1.4 SMT3115 Module Mechanical properties 20g34.1.5 SMT3729 Module Mechanical properties 21g34.1.6 SMT3722 Module Mechanical properties 24g34.1.7 SMT2522 Module

12、 Mechanical properties 26g34.1.8 SMT2515 Module Mechanical properties 28g34.1.9 SMT1922 Module Mechanical properties 29g34.1.10 SMT1915 Module Mechanical properties 31g34.2 Pad Size and Spacing . 33g34.3 Pad Assignments 35g35 Electrical Specifications . 38g35.0 Electrical Interfaces and Interface Fa

13、milies . 38g35.1 RF and UIM . 40g35.1.1 Electrical Characteristics of RF Interfaces 40g35.1.1.1 RF_1 40g35.1.1.2 RF_2 40g35.1.1.3 RF_3 40g35.1.1.4 RF_4 41g35.1.1.5 RF_GNSS . 41g35.1.1.6 RF_AUX . 41g35.1.2 User Identity Module 41g35.1.2.0 UIM Interface Introduction . 41g35.1.2.1 UIM_VCC . 41g35.1.2.2

14、 UIM_DATA 41g35.1.2.3 UIM_CLK. 41g35.1.2.4 UIM_RESET . 41g35.1.2.5 UIM_DETECT 41g35.1.2.6 UIM_SPU . 41g35.2 Data Interfaces 41g35.2.0 Data Interfaces Introduction . 41g35.2.1 Universal Asynchronous Receiver-Transmitter 42g35.2.1.0 2-wire, 4-wire, and 8-wire UART Configurations 42g35.2.1.1 UART_TX 42

15、g35.2.1.2 UART_RX 42g35.2.1.3 UART_RTS 42g35.2.1.4 UART_CTS 42g3ETSI ETSI GS SMT 001 V2.1.1 (2015-06)45.2.1.5 UART_DSR 42g35.2.1.6 UART_DCD . 42g35.2.1.7 UART_RING 42g35.2.1.8 UART_DTR 42g35.2.2 Universal Serial Bus 2.0 . 42g35.2.2.0 USB 2.0 Introduction 42g35.2.2.1 USB_Dp 42g35.2.2.2 USB_Dn 43g35.2

16、.2.3 VBUS 43g35.2.3 Universal Serial Bus 2.0 High-Speed Inter-Chip 43g35.2.3.0 USB 2.0 HSIC Introduction 43g35.2.3.1 USB_STROBE 43g35.2.3.2 USB_DATA 43g35.2.4 Universal Serial Bus 3.0 SuperSpeed Interfaces . 43g35.2.4.0 USB 3.0 SuperSpeed Introduction 43g35.2.4.1 USB3_SSTXp . 43g35.2.4.2 USB3_SSTXn

17、. 43g35.2.4.3 USB3_SSRXp . 43g35.2.4.4 USB3_SSRXn. 43g35.2.5 Peripheral Component Interconnect Express 43g35.2.5.0 PCIe Introduction 43g35.2.5.1 PCIe_Rp 43g35.2.5.2 PCIe_Rn 43g35.2.5.3 PCIe_Tp 43g35.2.5.4 PCIe_Tn 44g35.2.5.5 PCIe_REFCLKp . 44g35.2.5.6 PCIe_REFCLKn . 44g35.2.5.7 PCIe_RST . 44g35.2.5.

18、8 PCIe_CLKREQ . 44g35.2.5.9 PCIe_WAKE . 44g35.2.6 MIPI M-PHY 44g35.2.6.0 MIPI M-MPHY Introduction 44g35.2.6.1 MPHY_TX1-Dp 44g35.2.6.2 MPHY_TX1-Dn 44g35.2.6.3 MPHY_RX1-Dp . 44g35.2.6.4 MPHY_RX1-Dn . 44g35.2.6.5 MPHY_TX2-Dp 44g35.2.6.6 MPHY_TX2-Dn 44g35.2.6.7 MPHY_RX2-Dp . 44g35.2.6.8 MPHY_RX2-Dn . 44

19、g35.2.6.9 MPHY_SB1 45g35.2.6.10 MPHY_SB2 45g35.2.6.11 MPHY_SB3 45g35.2.6.12 MPHY_SB4 45g35.2.7 MIPI C-PHY . 45g35.2.7.0 MIPI C-PHY Introduction . 45g35.2.7.1 CPHY_LANE1_DATA_A . 45g35.2.7.2 CPHY_LANE1_DATA_B 45g35.2.7.3 CPHY_LANE1_DATA_C 45g35.2.7.4 CPHY_LANE2_DATA_A . 45g35.2.7.5 CPHY_LANE2_DATA_B

20、45g35.2.7.6 CPHY_LANE2_DATA_C 45g35.2.7.7 CPHY_LANE3_DATA_A . 45g35.2.7.8 CPHY_LANE3_DATA_B 45g35.2.7.9 CPHY_LANE3_DATA_C 45g35.2.7.10 CPHY_SB1 . 45g35.2.7.11 CPHY_SB2 . 46g35.2.7.12 CPHY_SB3 . 46g35.3 Module Control and State Functions 46g35.3.0 Module Control and State Functions Introduction 46g35

21、.3.1 WWAN_STATE . 46g35.3.2 POWER_ON. 46g3ETSI ETSI GS SMT 001 V2.1.1 (2015-06)55.3.3 WAKEUP_OUT . 48g35.3.4 WAKEUP_IN . 48g35.3.5 RESET 48g35.3.6 VREF 48g35.4 General Purpose . 48g35.4.0 GPP and GPIO Introduction . 48g35.4.1 General Purpose Input/Output (GPIO) . 49g35.4.2 General Purpose Pad (GPP)

22、49g35.4.3 Virtual GPIO (vGPIO) 49g35.5 Digital Audio 49g35.5.0 General Digital Audio Introduction 49g35.5.1 Pulse Code Modulation . 49g35.5.1.0 PCM Introduction . 49g35.5.1.1 PCM_SYNC 49g35.5.1.2 PCM_DIN . 49g35.5.1.3 PCM_DOUT . 49g35.5.1.4 PCM_CLK 49g35.5.2 Integrated Inter Chip Sound 49g35.5.2.0 I

23、2S Introduction 49g35.5.2.1 I2S_WS . 49g35.5.2.2 I2S_DIN 49g35.5.2.3 I2S_DOUT 50g35.5.2.4 I2S_CLK . 50g35.5.3 SLIMBus 50g35.5.3.0 SLIMBus Introduction 50g35.5.3.1 SLIM_CLK . 50g35.5.3.2 SLIM_DATA 50g35.6 Power, Ground and Digital Logic Levels . 50g35.6.1 Power Supply 50g35.6.1.1 VCC Pads 1 6 . 50g35

24、.6.1.2 RTC_POWER . 50g35.6.2 Ground 50g35.6.3 Reference Voltage and Digital Logic Levels 51g35.6.3.1 VREF 51g35.7 Test and Debug Interface . 52g35.8 Reserved for Future Use (RFU) . 52g3Annex A (informative): Interfaces that may be provided over General Purpose I/O (GPIO) or General Purpose Pads (GPP

25、) 53g3A.0 GPIO and GPP Interfaces Introduction 53g3A.1 Additional Interfaces 53g3A.1.0 Additional Interfaces Introduction . 53g3A.1.1 Module State Functions 53g3A.1.1.0 Additional Module Control and State Functions Introduction 53g3A.1.1.1 RF_DISABLE . 53g3A.1.1.2 GNSS_STATE 53g3A.1.1.3 PER1_STATE .

26、 53g3A.1.1.4 TX_ON . 53g3A.1.1.5 READY 53g3A.1.2 Analog Interfaces . 54g3A.1.2.0 Analog Interfaces Introduction . 54g3A.1.2.1 Analog Audio 54g3A.1.2.2 A/D Converter 54g3A.1.2.3 D/A Converter 54g3A.1.3 Host interface select . 54g3A.1.4 Antenna control 54g3A.1.5 Real Time Clock . 55g3A.1.6 Pulse Width

27、 Modulation . 55g3A.1.7 Timer Interface . 55g3A.1.8 Interrupt 55g3ETSI ETSI GS SMT 001 V2.1.1 (2015-06)6A.1.9 Dynamic Power Reduction . 55g3A.1.10 Virtual GPIO (vGPIO) . 55g3A.2 Peripheral Interfaces . 55g3A.2.0 Peripheral Interfaces Introduction 55g3A.2.1 Secure Digital Input Output Interface 56g3A

28、.2.2 Inter Integrated Circuit Interface 56g3A.2.3 Serial Peripheral Interface 56g3A.2.4 Controller Area Network Bus . 56g3Annex B (informative): Design guidelines and recommendations . 57g3B.1 Recommendations from ETSI ISG SMT on how to use the present document . 57g3B.2 Host PCB Pad Layouts . 57g3B

29、.2.0 Host PCB Pad Layouts Introduction 57g3B.2.1 SMT3136 Module PCB Pad Layout . 57g3B.2.2 SMT3129 Module PCB Pad Layout . 58g3B.2.3 SMT3122 Module PCB Pad Layout . 59g3B.2.4 MT3115 Module PCB Pad Layout . 60g3B.2.5 SMT3729 Module PCB Pad Layout . 60g3B.2.6 SMT3722 Module PCB Pad Layout . 61g3B.2.7

30、SMT2522 Module PCB Pad Layout . 61g3B.2.8 SMT2515 Module PCB Pad Layout . 62g3B.2.9 SMT1922 Module PCB Pad Layout . 62g3B.2.10 SMT1915 Module PCB Pad Layout . 62g3B.2.11 SMT3136, SMT3129, and SMT3122 Common PCB Pad Layout . 63g3B.2.12 SMT3729 and SMT3722 Common PCB Pad Layout 64g3B.2.13 SMT2522 and

31、SMT2515 Common PCB Pad Layout 65g3B.2.14 Minimal SMT1915 and SMT2515 Common PCB Pad Layout 65g3B.2.15 Minimal SMT1915, Minimal SMT2515, and SMT3115 Common PCB Pad Layout 66g3B.3 Reserved for Future Use (RFU) Pads on Host PCB . 67g3B.4 Advanced Indicator Protocols for WWAN_STATE 67g3B.5 Recommendatio

32、ns for RESET Implementation . 67g3Annex C (informative): Bibliography . 68g3History 69g3ETSI ETSI GS SMT 001 V2.1.1 (2015-06)7Intellectual Property Rights IPRs essential or potentially essential to the present document may have been declared to ETSI. The information pertaining to these essential IPR

33、s, if any, is publicly available for ETSI members and non-members, and can be found in ETSI SR 000 314: “Intellectual Property Rights (IPRs); Essential, or potentially Essential, IPRs notified to ETSI in respect of ETSI standards“, which is available from the ETSI Secretariat. Latest updates are ava

34、ilable on the ETSI Web server (http:/ipr.etsi.org). Pursuant to the ETSI IPR Policy, no investigation, including IPR searches, has been carried out by ETSI. No guarantee can be given as to the existence of other IPRs not referenced in ETSI SR 000 314 (or the updates on the ETSI Web server) which are

35、, or may be, or may become, essential to the present document. Foreword This Group Specification (GS) has been produced by ETSI Industry Specification Group (ISG) Surface Mount Technique (SMT). Modal verbs terminology In the present document “shall“, “shall not“, “should“, “should not“, “may“, “need

36、 not“, “will“, “will not“, “can“ and “cannot“ are to be interpreted as described in clause 3.2 of the ETSI Drafting Rules (Verbal forms for the expression of provisions). “must“ and “must not“ are NOT allowed in ETSI deliverables except when used in direct citation. Introduction The goal of the pres

37、ent document is to specify a form factor for Surface Mount Technology (SMT) based communication modules for devices supporting services across multiple vertical markets and not one specific market segment. The present document reflects the current state for M2M and connected device design and attemp

38、ts to address future needs. ETSI ETSI GS SMT 001 V2.1.1 (2015-06)81 Scope This present document proposes mechanical and electrical requirements for wireless module implementations. This includes the SMT pad layout and common interface assignments for essential pads including some general electrical

39、characteristics. Certain aspects such as z-height, shielding geometry and weight are not defined by the present document. The SMT module pad configurations defined in the present document are primarily intended to allocate specific pad functionalities that need to be routed on the host device to the

40、 respective pads on the SMT module. Although many interfaces may be defined in the various pad configurations, it does not necessarily imply that all interfaces need to be supported at the same time. The assigned allocations are intended to enable the module supplier and host device integrator to de

41、sign compatible circuits with aligned pad assignments as specified. 2 References 2.1 Normative references References are either specific (identified by date of publication and/or edition number or version number) or non-specific. For specific references, only the cited version applies. For non-speci

42、fic references, the latest version of the referenced document (including any amendments) applies. Referenced documents which are not found to be publicly available in the expected location might be found at http:/docbox.etsi.org/Reference. NOTE: While any hyperlinks included in this clause were vali

43、d at the time of publication, ETSI cannot guarantee their long term validity. The following referenced documents are necessary for the application of the present document. 1 ISO/IEC 7816-3: “Identification cards - Integrated circuit cards - Part 3: Cards with contacts - Electrical interface and tran

44、smission protocols“. 2 ETSI TS 102 221: “Smart Cards; UICC-Terminal interface; Physical and logical characteristics“. 3 USB 2.0 Specification (April 2000): “Universal Serial Bus Specification, Revision 2.0“. NOTE: Available from http:/www.usb.org/developers/docs/usb20_docs. 4 USB 2.0 Specification:

45、“HSIC - High-Speed Inter-Chip USB Electrical Specification“, Version 1.0 (September 23, 2007), plus HSIC ECN Disconnect Supplement to High-Speed Inter-Chip Specification Revision 0.94 (September 20, 2012). 5 USB 3.1 Specification (July 2013): “Universal Serial Bus 3.1 Specification“. NOTE: Available

46、 from http:/www.usb.org/developers/docs/. 6 PCI-SIG: “PCI Express M.2 Specification“, Revision 1.0, December 12, 2013. NOTE: Available from https:/ 7 mipi alliance: “M-PHY Specification“, version 2.0, April 4, 2012. NOTE: Available from http:/mipi.org/specifications/physical-layer. 8 ETSI TS 124 008

47、: “Digital cellular telecommunications system (Phase 2+); Universal Mobile Telecommunications System (UMTS); LTE; Mobile radio interface Layer 3 specification; Core network protocols; Stage 3 (3GPP TS 24.008 Release 12)“. 9 mipi alliance: “Serial Low-power Inter-chip Media Bus (SLIMbus) Specificatio

48、n“. NOTE: Available from http:/mipi.org/specifications/serial-low-power-inter-chip-media-bus-slimbussm-specification. ETSI ETSI GS SMT 001 V2.1.1 (2015-06)910 IEEE 1149.1: “IEEE Standard for Test Access Port and Boundary-Scan Architecture“. (Joint Test Action Group, or JTAG). 11 SD Card Association:

49、 “SD Specifications Part 1 - Physical Layer - Simplified Specification“ Version 3.01, 2010. 12 SD Card Association: “SD Specifications Part 1 - Physical Layer - Simplified Specification“ Version 4.10, 2013. 13 ISO 11898-1:2003: “Road vehicles - Controller area network (CAN) - Part 1: Data link layer and physical signalling“. NOTE: Available from http:/www.iso.org/iso/iso_catalogue/catalogue_tc/catalogue_detail.htm?csnumber=33422. 14 C-PHY Specification, version 1.0, October