ECA EIA-448-24-1994 Test Method 24 Solid State Switch Transfer Tests.pdf

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1、 EIA 448-24 74 3234600 0555583 5T AUGUST 1994 f AMERKAN L STANDARD ANSI/ EIA- 448- 2 4- 19 93 APPROVED: November 12, 1993 EIA STANDARD Test Method 24 Solid State Switch Transfer Tests EIA-448-24 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT EIA 448-24 94 m 3234600 0555582 796 m NOTICE EIA

2、 Engineering Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the pro

3、per product for his particular need. Existence of such Standards and Publications shall not in any respect preclude any member or nonmember of EIA from manufacturing or selling products not conforming to such Standards and Publications, nor shall the existence of such Standards and Publications prec

4、lude their voluntary use by those other than EIA members, whether the standard is to be used either domestically or internationally. Recommended Standards and Publications are adopted by EIA in accordance with the American National Standards Institute (ANSI) patent policy. By such action, EIA does n

5、ot assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the Recommended Standard or Publication. This EIA Standard is considered to have International Standardization implication, but the International Electrotechnical Commission activity has not p

6、rogressed to the point where a valid comparison between the EIA Standard and the IEC document can be made. This Standard does not purport to address all safety problems associated with its use or all applicable regulatory requirements. It is the responsibility of the user of this Standard to establi

7、sh appropriate safety and health practices and to determine the applicability of regulatory limitations before its use. Published by ELECTRONIC INDUSTRIES ASSOCIATION 1994 Engineering Department 2001 Pennsylvania Ave. N.W., Washington, D.C. 20006 PRICE: Please refer to the current Catalog of EIA, JE

8、DEC, and TIA STANDARDS and ENGINEERING PUBLICATIONS or call Global Engineering Documents, USA and Canada (I -800-854-7179) Intemational (303-397-7956) All rights reserved Printed in U.S.A. PLEASE! DONTVIOLATE THE JAW! . This dmment is copyrighted by the EM and may not be reproduced without permissio

9、lL Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement with the ETA. For information, contact. EL4 Engineering .hbXcations Office 2001 Pennsylvania Ave., N.W. Washington, D.C,.20006 (202)457-4963 EIA-448-24 Page 1 STANDARD TEST METHOD

10、 24 SOLID STATE SWITCH TRANSFER TESTS (From EIA Standards Proposal No. 2382, formulated under the cognizance of the EIA P-13 Committee on Switches.) 1 Purpose The purpose of this test method is to establish a standard for measuring the transfer time of switches with solid state cirait outputs. This

11、standard applies to devices such as manually operated solid state switches, sensors with solid state outputs, or controllers interfacing between multiple switch arrays and computer processors. 2 Definitions As they relate to the requirements of this document, the following definitions shall apply (f

12、igures 1 through 3 graphically represent the timing relationships): solid state switch transfer time The time interval between the instant when switch-actuating sensor detects the switching command and the instant when the output of the switching element has changed state. NOTE - Typical times are m

13、easured in milliseconds or microseconds. Transfer time is represented by tr in figure 1. rise time The interval between the instant when the switch output transistor first reaches the specified lower limit and the instant when it reaches the specified upper limit. NOTE - Unless otherwise specified,

14、these limits are the 10% and 90% points of the upper limit. Typical times are measured in nanoseconds. Rise time is represented by tR in figures 1,2 and 3. fall time The interval between the instant when the switch output amplitude first reaches the upper limit and the instant when it reaches the sp

15、ecified lower limit. NOTE - Fall time is essentially the inverse of rise time. Typical times are measured in nanoseconds. Fail time is represented by t, in figure 1. - - - EIA 448-24 94 m 3234LOO 0555585 4T5 m ,- EIA-448-24 Page 2 momentary switch pulse output May be either a fixed time for each act

16、uation (a pulse) or simply the time that a momentary switch is manuaily held down or mechanically actuated. In other words, it is the interval between turn-on and turn-off transitions. When measured, the time is defined as the interval between the leading and trailing edges of the output signal and

17、measured at points which bear a specified relation to the maximum value of the pulse. Unless otherwise specified, it shall be measured at the 50% points of the transitions. The measurement the of a pulse output is illustrated in figure 1. switching sensor A transducer that detects a parameter (such

18、as manua displacement or position sensing) and converts that parameter into a form (such as a voltage or current signai) suitable to accomplish the switching action. time delay A time interval that is purposely introduced to ensure that the switch sensor (or electromechanical element) has settled an

19、d that the solid state output will not contain spurious pulses due to the equivalent of contact bounce. NOTE - Typical times are measured in milliseconds or microseconds. Delay time is represented by t, in figure 1. overshoot Thai part of a distorted signal output following switching action characte

20、rized by a rise above (or fd below) the final value, followed by a decaying return to the final value. Such a signal is shown in figure 3. settling time Following the switching action, the time required for the output to enter, and remain Within, a specified narrow band centered on its final steady-

21、state value; unless otherwise specified, this band shall be l?! of its final value. Settling time is represented by t, in figure 3. Switch transfer is not considered complete until the output has settled to within the tolerance band of its final value. 3 Requirements 3.1 Load O All switch transfer t

22、iming tests are to be conducted at maximum rated load current of the detailed specification. Unless otherwise specified, loads shall be unipolar (Le., direct current) and not bipolar (alternating current) type. For uniformity and repeatability of this test method, only resistive loads EIA-448 -24 Pa

23、ge 3 shall be used. (This should eliminate concern with overshoot, undershoot and spurious transients.) 3.2 Short-circui Uoverld protection When specified as an included feature of the device to be tested, short-circuit andfor overload protection shall be tested. 3.3 Bounce Unless allowed by the det

24、aiied specification, there shall be no bounce-like characteristic of the output circuit. Once the output has reached the intended ON (or om;.) state, including any allowable overshoot and settling, it shall not momentarily return to an OFF (or ON) state before again settling at the intended output c

25、ondition. 3.4 Switch transfer time The transfer time shall be measured in such a manner as to include the time from initial actuation of the sensing device to the time that the output signal has stabilized, and it shall include any delay or blanking time inherent in the device used to ensure that th

26、e sensor response and settling times are not transmitted to the output. 3.5 Switch output transition times Unless otherwise specified, output rise time and fall time from 10% to 90% of final value. 3.6 Switch actuation Unless otherwise specified, the switch mechanism which causes contact transfer sh

27、all be actuated at a velocity as follows: (a) Sensitive Switches: 25 mm/s max. (1.0 ids max.) (b) Pushbutton Switches: 76 to 127 4s (3 to 5 ids) 4 Procedure 4.1 Mounting The switch under test shall be mounted by its normal mounting means to a structure of sufficient mass that it be considered resona

28、nce-free. 4.2 Load connections for test circuits To prevent undesirable ground loops, all power supplies, drivers and measuring equipment shall have EIA-448-24 Page 4 a common electrical ground. 4.2.1 4.2.2 4.2.3 4.3 A simplified schematic of the connections of a low-side driver, or current sinking

29、coniguration, is shown in figure 4. (Solid state output circuits in this configuration often have common grounded emitters or sources.) Shown in figure 5 is a simpEed schematic of the connections of a high side driver, or current sourcing configuration. (Solid state output circuits in this configura

30、tion often have internally biased common collectors.) Unless otherwise specsed in the detailed specification, solid state output circuits with uncommitted collectors and emitterdsources may be connected in either configuration, as shown in figure 6. For the purposes of this test method, this type of

31、 circuit should be connected in a manner that represents the planned application. Circuit transfer test setup The test circuit shown in figure 7, or an equivalent, shall be used for making solid state switch circuit transfer measurements. 4.4 Short-circuit/overload protection The foliowing test meth

32、ods apply to switches that are specified to have short-circuit and/or overload protection. For overload and short circuit testing, the power supply current rating and Wiring resistance (Wire she) should be sufficient to accommodate the intended test current levels. 4.4.1 4.4.2 Method I: For combined

33、 short-circuit and overload protection testing, when applicable, the procedure is to short across the load resistance in the test setup. The power supply current may be monitored, ifdesired, veriwng operation under normal load and then observing the ment surge preceding device shutdown. Remove the s

34、hort circuit and veri proper switch operation. Method II: For overload protection testing, place a shunting resistance, on a temporary basis, in parallel with the load resistance. The value of the total load shall be such as to provide sufficient overload current to reach the overload protection tri

35、p point. Monitor the switch output to observe circuit shutdown. Remove the parallel overload resistance and ver proper switch operation. EIA-448-24 Page 5 4.5 Test measurement equipment 4.5.1 The detection and display means (oscilloscope, logic analyzer, or equivalent) utilized in the Circuit shall

36、have a bandwidth of 10 megahertz or greater, a minimum time base accuracy of - + 5 %, and shall be capable of showing the quiescent state of the output prior to switch actuation. 4.5.2 Unless otherwise sed &the detailed specification, the actuating mechanism shall provide the velocities as specified

37、 above. EIA-44 8 -24 Page 6 VOLTS +-PULSE VIJIDTH u I I Figure 1 TIMING RELATIONSHIPS FOR SOLID STATE SWITCH TRANSFER MEASUREMENTS EIA 448-24 94 W 3234b00 0555590 8b2 EIA-448-24 Page 7 VOLTS 110% .T- - 90% -o- - 1 I I I I I I TIME * I I 10% L/ I 1 et* Figure 2 I. TYPICAL SWITCH OUTPUT WITH RESISTIVE

38、 LOAD OR CRITICALLY DAMPED OUTPUT CIRCUIT VOLTS A 110% I 90% - 10% -1- - - - - - -t- 1 1 1 I I I TIME * 7 I tR I I Figure 3 TYPICAL SWITCH OUTPUT WITH INDUCTIVE LOAD OR UNDEIUWlPED OUTPUT CIRCUIT EIA-448-24 Page 8 POWER T I LOD Figure 4 LO W-SI0 E D RIVER CON FIG UR AT10 N POLIER T .OAD vc I TI Figure 5 HIGH-SIDE DRIVER CONFIGURATION POWER -r Figure 6 UNCOMMITTED DRIVER OPTIONAL CONFIGURATIONS SW I TCH UNDER TEST I r wm POWER STOIWT Figure 7 - - TEST CIRCUIT SETUP