DLA SMD-5962-96509 REV B-2013 MICROCIRCUIT MEMORY DIGITAL CMOS 512 X 18 X 2 FIFO MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DAY) APPROVED A Boilerplate update and part of five year review. tcr 06-03-14 Raymond Monnin B Update drawing to meet current MIL-PRF-38535 requirements. Removed class M references. - glg 13-12-13 Charles Saffle REV SHEET REV B B B B B B SHEET 15 16 17 18 19 20

2、 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY

3、 All DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Michael. A. Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 512 X 18 X 2 FIFO, MONOLITHIC SILICON DRAWING APPROVAL DATE 95-11-09 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-96509 SHEET 1 OF 20 DSCC FORM 2233 APR 97 5962-E091-

4、14 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-96509 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product a

5、ssurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) le

6、vels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 96509 01 Q X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1

7、RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A da

8、sh (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54ABT7820 512 X 18 X 2 FIFO 1.2.3 Device class designator. The device class designator is a single letter identifying the product assur

9、ance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA15 - 84 84 Pi

10、n grid array 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-965

11、09 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc DC input voltage range (VIN) . -0.5 V dc to VCC+ 0.5 V dc 4/ DC output voltage range (VOUT) . -0.5 V dc to +5.5 V dc 4/ DC output current (IOL) (per output) . +4

12、8 mA DC input clamp current (IIK) (VIN 0.0 V ) -18 mA DC output clamp current (IOK) (VOUT 0.0 V) . -50 mA Storage temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 10 seconds) +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C Maxim

13、um power dissipation (PD) . 500 mW 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Input voltage range (VIN) +0.0 V dc to VCCMaximum low level input voltage (VIL) 0.8 V Minimum high level input voltage (VIH) . 2.0 V Maximum high level output current (IOH

14、) -12 mA Maximum low level output current (IOL) +24 mA Maximum input rise or fall rate (t/V) 5 ns/V Case operating temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part

15、of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARD

16、S MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available onl

17、ine at http:/quicksearch.dla.mil/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance

18、 and affect reliability. 2/ Unless otherwise noted, all voltages are referenced to GND. 3/ The limits for the parameters specified herein shall apply over the full specified VCCrange and case temperature range of -55C to +125C. 4/ The input negative voltage rating may be exceeded provided that the i

19、nput clamp current rating is observed. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-96509 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government p

20、ublications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. JEDEC INTERNATIONAL (JEDEC) JESD 78 - IC Latch-Up Test. (Applications for copies should

21、 be addressed to JEDEC, 3103 North 10thStreet, Suite 240-S, Arlington, VA 22201-2107; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through lib

22、raries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific ex

23、emption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan sha

24、ll not affect the form, fit, or function as described herein 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outlines. The case outlines shall be in accordanc

25、e with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3

26、.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrica

27、l test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packa

28、ges where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance wi

29、th MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer

30、 in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the require

31、ments of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted

32、without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-96509 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordan

33、ce with MIL-PRF-38535 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be

34、 conducted on all devices prior to qualification and technology conformance inspection. 4.2.1 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturers QM plan in accor

35、dance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit sh

36、all specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requi

37、rements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535

38、and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-96509 REVISION LEVEL B SHEET 6 DS

39、CC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device types Group A subgroups Limits 2/ Unit Min Max High level output voltage VOHFor all inputs affecting output under test VIN= 2.0 V or 0

40、.8 V IOH= -3.0 mA VCC= 4.5 V All 1, 2, 3 2.5 V IOH= -3.0 mA VCC= 5.0 V All 1, 2, 3 3.0 IOH= -12.0 mA VCC= 4.5 V All 1, 2, 3 2.0 Low level output voltage VOLFor all inputs affecting output under test, VIN= 2.0 V or 0.8 V, IOL= 24 mA VCC= 4.5 V All 1, 2, 3 0.55 V Negative input clamp voltage VIC-For i

41、nput under test, IIN= -18 mA VCC= 4.5 V All 1, 2, 3 -1.2 V Input current II3/ For input under test, VI= VCCor GND, VCC= 5.5 V All 1, 2, 3 5 A Three-state output leakage current high IOZH3/ For control input affecting output under test, VIN= 2.0 V or 0.8 V VOUT= 2.7 V, VCC= 5.5 V All 1, 2, 3 50 A Thr

42、ee-state output leakage current low IOZL3/ For control input affecting output under test, VIN= 2.0 V or 0.8 V VOUT= 0.5 V, VCC= 5.5 V All 1, 2, 3 -50 A Output current IO4/ VOUT= 2.5 V, VCC= 4.5 V All 1, 2, 3 -40 -180 mA Quiescent supply current, outputs high ICCHFor all inputs, VIN= VCCor GND IOUT=

43、0 A, VCC= 5.5 V All 1, 2, 3 15 mA Quiescent supply current, outputs low ICCLALl 1, 2, 3 95 mA Quiescent supply current, outputs disabled ICCZAll 1, 2 ,3 15 mA Control Input capacitance CINTC= +25C See 4.4.1b VCC= 5.0 V Control inputs All 4 10.5 pF I/O capacitance CI/OA or B ports All 4 14.5 pF See f

44、ootnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-96509 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance c

45、haracteristics Continued. Test Symbol Test conditions 1/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device types Group A subgroups Limits 2/ Unit Min Max Functional test 5/ VIH= 2.0 V, VIL= 0.8 V Verify output VO See 4.4.1c, VCC= 4.5 V and 5.5 V All 7, 8A, 8B L H 7, 8A, 8B L H Pulse

46、duration tw1CL= 50 pF minimum, RL= 500 VCC= 4.5 V and 5.5 V See figure 3 as applicable LDCKA, LDCKB high All 9, 10, 11 9 ns tw2LDCKA, LDCKB low All 9, 10, 11 9 tw3UNCKA, UNCKB high All 9, 10, 11 9 tw4UNCKA, UNCKB low All 9, 10, 11 9 tw5RSTA , RSTB low All 9, 10, 11 10 Setup time tsu1A0-A17 before LD

47、CKA and B0-B17 before LDCKB All 9, 10, 11 4 tsu2PENA before LDCKA and PENB before LDCKB All 9, 10, 11 6 tsu3LDCKA inactive before RSTA high and LDCKB inactive before RSTB high All 9, 10, 11 4 Hold time th1A0-A17 after LDCKA and B0-B17 after LDCKB All 9, 10, 11 0 th2PENA after LDCKA low and PENB afte

48、r LDCKB low All 9, 10, 11 3 th3LDCKA inactive after RSTA high and LDCKB inactive after RSTB high All 9, 10, 11 4 Max operating frequency fMAXAll 9, 10, 11 40 MHz See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-96509 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 T