DLA SMD-5962-94760 REV B-2008 MICROCIRCUIT MEMORY DIGITAL CMOS ELECTRICALLY ERASABLE PROGRAMMABLE LOGIC DEVICE MONOLITHIC SILICON《数字记忆单硅片微电路 由互补金属氧化物半导体结构组成 带电可擦可编程逻辑装置》.pdf

《DLA SMD-5962-94760 REV B-2008 MICROCIRCUIT MEMORY DIGITAL CMOS ELECTRICALLY ERASABLE PROGRAMMABLE LOGIC DEVICE MONOLITHIC SILICON《数字记忆单硅片微电路 由互补金属氧化物半导体结构组成 带电可擦可编程逻辑装置》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-94760 REV B-2008 MICROCIRCUIT MEMORY DIGITAL CMOS ELECTRICALLY ERASABLE PROGRAMMABLE LOGIC DEVICE MONOLITHIC SILICON《数字记忆单硅片微电路 由互补金属氧化物半导体结构组成 带电可擦可编程逻辑装置》.pdf（16页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. - gap 02-04-17 Raymond Monnin B Boilerplate update, part of 5 year review. ksr 08-06-10 Robert M. Heber REV SHET REV B SHET 15 REV STATUS REV B B B B B B B B B B B B B B OF SHE

2、ETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael Frye AND AGENCIE

3、S OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 94-12-21 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, ELECTRICALLY ERASABLE PROGRAMMABLE LOGIC DEVICE, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-94760 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E397-08 Provided by IHSNot for R

4、esaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94760 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class lev

5、els consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected

6、 in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 94760 01 M X C Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Devi

7、ce classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a n

8、on-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Maximum Device type Generic number Circuit function clock frequency 01 pLSI1024 EECMOS 4,000 gate 60 MHz programmable logic device 1.2.3 Device class designator. The device class designator is a single

9、letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification

10、 to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CQCC2-J68 68 J-Leaded chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q a

11、nd V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94760 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR

12、 97 1.3 Absolute maximum ratings. 1/ Supply voltage range -0.5 V dc to +7.0 V dc Input voltage range (applied) -2.5 V dc to VCC+ 1.0 V dc Off-state output voltage range applied. . -2.5 V dc to VCC+ 1.0 V dc Thermal resistance, junction-to-case (JC) See MIL-STD-1835 Maximum power dissipation (PD) 2/

13、. 2.1 W Maximum junction temperature . +175C Lead temperature (soldering, 10 seconds max) +300C Data retention (at +55C) 20 years (minimum) Endurance . 100 erase/write cycles (minimum) 1.4 Recommended operating conditions. Supply voltage range, VCC . 4.5 V dc to 5.5 V dc High level input voltage ran

14、ge (VIH) . 2.0 V dc to VCC+ 1.0 V dc Low Level input voltage range (VIL) . 0.0 V dc to 0.8 V dc Case operating temperature range, TC -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this

15、 drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-S

16、TD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at

17、http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, th

18、e issues of these documents are those cited in the solicitation. ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.

19、org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between t

20、he text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Stresses above the absolute maximum rating may cause permanent damage

21、to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Must withstand the added PDdue to short circuit test; e.g., IOS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING

22、SIZE A 5962-94760 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modifie

23、d in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and

24、 as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline sha

25、ll be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth tables. The truth tables shall be as specified on figure 2. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no alt

26、ered item drawing shall be as specified on figure 2. When required in screening (see 4.2 herein), or qualification conformance inspection groups A, B, C, or D (see 4.3 herein), the devices shall be programmed by the manufacturer prior to test. 3.2.3.2 Programmed devices. The truth table for programm

27、ed devices shall be as specified by an attached altered item drawing. 3.2.4 Functional block diagram. The functional block diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical per

28、formance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each su

29、bgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not mark

30、ing the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance m

31、ark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be

32、 required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). Th

33、e certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, app

34、endix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for devic

35、e class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activ

36、ity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in mi

37、crocircuit group number 42 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94760 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 22

38、34 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Min Max Units Low level output voltage VOLIOL= 8.0 mA, VIL= 0.8 V, VCC= 4.5 V 1, 2, 3 0.4 V High level output voltage VOHIOH= -4.0 mA, V

39、IL= 0.8 V, VCC= 4.5 V 1, 2, 3 2.4 V Low level input voltage VIL1/ 1, 2, 3 0.8 V High level input voltage VIH1/ 1, 2, 3 2.0 V Input or I/O low leakage current IIL0 V VIN 0.8 V 1, 2, 3 -10 A Input or I/O high leakage current IIH3.5 V VIN VCC1, 2, 3 10 A I/O active pull-up current 2/ IPU0 V VIN VIL1, 2

40、, 3 -150 A Output short circuit current 3/ IOSVOUT= 0.5 V, VCC= 5.0 V, TA= +25C, see 4.4.1f 1 -60 -200 mA Operating power supply current 4/ ICCVIL= 0.5 V, VIH= 3.0 V, f = 1.0 MHz 1, 2, 3 215 mA Dedicated input capacitance CINVIN= 2.0 V, VCC= 5.0 V, TA= +25C, f = 1.0 MHz, see 4.4.1e 4 10 pF I/O and c

41、lock capacitance CI/O, CYVI/O, VY= 2.0 V, VCC= 5.0 V, TA= +25C, f = 1.0 MHz, see 4.4.1e 4 10 pF Functional tests See 4.4.1c 7, 8A, 8B Data propagation delay, 4PT bypass, ORB bypass tPD19, 10, 11 20 ns Data propagation delay, worst case path tPD29, 10, 11 25 ns Clock frequency with internal feedback

42、7/ fMAX19, 10, 11 60 MHz Clock frequency with external feedback 8/ fMAX29, 10, 11 38 MHz Clock frequency, maximum toggle 9/ fMAX3VCC= 4.5 V, see figure 4 5/ 6/ 9, 10, 11 83 MHz See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IH

43、S-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94760 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Limits Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise spec

44、ified Group A subgroups Min Max Units GLB register setup time before clock, 4PT bypass tSU19, 10, 11 9 ns GLB register clock to delay, ORP bypass tCO19, 10, 11 13 ns GLB register hold time after clock, 4PT bypass tH19, 10, 11 0 ns GLB register setup time before clock tSU29, 10, 11 13 ns GLB register

45、 clock to output delay tCO29, 10, 11 16 ns GLB register hold time after clock tH29, 10, 11 0 ns External reset pin to output delay tR9, 10, 11 22.5 ns External reset pulse duration tRPW9, 10, 11 13 ns Input to output enable tPZH, tPZL9, 10, 11 24 ns Input to output disable tPHZ, tPLZ9, 10, 11 24 ns

46、External synchronous clock pulse duration, high tPWH9, 10, 11 6 ns External synchronous clock pulse duration, low tPWL9, 10, 11 6 ns I/O register setup time before external synchronous clock (Y2, Y3) tSU5VCC= 4.5 V, see figure 4 5/ 6/ 9, 10, 11 2.5 ns I/O register hold time after external synchronou

47、s clock (Y2, Y3) tH59, 10, 11 8.5 ns 1/ These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2/ Pull-up circuitry is programmable. 3/ One output at a time for a maximum duration of one second. VOUT= 0.5 V was selected to avoid test pr

48、oblems by tester ground degradation. If not tested, shall be quaranteed to the limits specified in table I. 4/ Measured using six 16-bit counters. 5/ AC tests are performed with input rise and fall times (10% to 90%) of 3.0 ns, timing reference levels of 1.5 V, input pulse levels of 0 V to 3.0 V, and the output load of figure 4. Input pulse levels are absolute values with respect to device ground and all overshoots due to system or tester noise are included. Unless otherwise specified, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. 6/ May not be tested di