DLA SMD-5962-94642-1994 MICROCIRCUIT DIGITAL CMOS ENHANCED MULTI-FUNCTIONAL PERIPHERAL MONOLITHIC SILICON《硅单片 扩展多功能外围 氧化物半导体数字微型电路》.pdf

《DLA SMD-5962-94642-1994 MICROCIRCUIT DIGITAL CMOS ENHANCED MULTI-FUNCTIONAL PERIPHERAL MONOLITHIC SILICON《硅单片 扩展多功能外围 氧化物半导体数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-94642-1994 MICROCIRCUIT DIGITAL CMOS ENHANCED MULTI-FUNCTIONAL PERIPHERAL MONOLITHIC SILICON《硅单片 扩展多功能外围 氧化物半导体数字微型电路》.pdf（46页珍藏版）》请在麦多课文档分享上搜索。

1、SMD-5962-94642 9999996 D63046 900 fWISIOE 567 Fa/ WET 111 567 RVIIC N/A STANMDIZHI MILITARY DRANIm THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC NIA PREPARED BY Thomas M. Hess CHECKED BY Thomas M. Hess APPROVED BY Thomas M. Hess DRAWING APPROVAL

2、DATE 94- 08-24 REVISION LEVEL DEFE3GE ELECFOlICS WLY CHVIEFI wm, CHIO 45444. MICROCIRCUIT, DIGITAL, CMOS, ENHANCED MULTI-FUNCTIONAL PERIPHERAL, MONOLITHIC SILICON IzE A I- 67268 I 5962-94642 SHEFT 1 OF 45 )ESC FORM 193 JUL 91 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unl

3、imited. 5962-E308-94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-, SMD-5962-9Q642 9999996 0063047 847 M 1. SCOPE STANDARD1 ZED SIZE MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 1.1 scope. This drawing forms a part of a

4、one part - one part nuiiber docmentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes Q and M) and space application (device class V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Iden

5、tifying Nunber (PIN). 1.2.1 of MIL-STD-883, “Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices“. available, a choice of Radiation Harbiess Assurance (RHA) levels are reflected in the PIN. Device class M microcircuits represent non-JAN class B microcircuits in accord

6、ance with When 1.2 pIw. The PIN shall be as shown in the following exanple: 59 , 94642 r i 1 1 Federal RHA Device Device Case Lead stock class designator type class outline f inish designator (see 1.2.1) (see 1.2.2) des i gnat or (see 1.2.4) (see 1.2.5) LA (see 1.2.3) V Drawing nunber 1.2.1 RHA desi

7、gnator. Device class M RHA marked devices shall meet the MIL-1-38535 appendix A specified RHA levels and shall be marked with the appropriate RHA designator. MIL-1-38535 specified RHA levels and shall be marked with the appropriate RHA designator. non-RHA device. Device classes Q and V RHA marked de

8、vices shall meet the A dash (-) indicates a 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic nunber Circuit function o1 68902A 33 MHz enhanced multi-function peripheral 1.2.3 Device class designator. The device class designator shall be a s

9、ingle letter identifying the product assurance level as follows: Device class Device reauirements docwntation 5962-94642 fEVISIcNLML S-EET 2 M Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 Q or V Certification and qualificatio

10、n to MIL-1-38535 1.2.4 Case outline(s1. The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter DeSCriDtiVe desiqnator Termina 1s Packaqe style 2 Y CMGA3-Pl21 See figure 1 68 68 Pin grid array Gullwing-Lead chip carrier 1.2.5 Lead finish. The lead finish shall be as

11、 specified in MIL-STD-883 (see 3.1 herein) for class M or MIL-1-38535 for classes P and V. designation is for use in specifications when lead finishes A, B, and C are considered acceptable and interchangeable without preference. Finish letter llXll shall not be marked on the microcircuit or its pack

12、aging. The “X“ Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SflD-5962-94642 = 9999996 0063048 783 I 1.3 Absolute maxim ratings. I/ z/ STANDARD1 ZED SIIE MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CEWTER DAYTON, OHIO 45444 FEVISICNLML Supply vol

13、tage range (V,) Input voltage range (V,) . Output voltage range (VOUT) DC current drain per pin; DC current drain per pin; DC current drain; any single input or output . any single parallel outputs . V, and V, . Storage temperature range (TsTG) . Lead temperature (soldering, 10 seconds) . Junction t

14、emperature (T,) . Pouer dissipation (P,) Thermal resistance, junction-to-case (Ox) casez . caseY . 5962-94642 SET 3 -0.5 V dc to +7.0 V dc -1.5 V dc to V, +1.5 V dc -0.5 V dc to V, +0.5 V dc 50 IrA 100 ln4 Ella -65C to +15OoC +30Ooc +175OC 1.5 U See MIL-STD-1835 1.5 “C/U I 1.4 Recomnended operating

15、conditions. Supply voltage range (VD,) input voltage (V,) Output voltage (VouT) . Case operating tenperature range (T,) . -55C to +125“C -0.5 V dc to +7.0 V dc -1.5 V dc to V, +1.5 V dc -1.5 V dc to V, +1.5 V dc 1.5 Digital loqic testing for device classes O and V. Fault coverage measurement of manu

16、facturing logic tests (MIL-STD-883, test method 5012) XX percent s/ 2. APPLICABLE DOCUMENTS 2.1 Govermient swcification, standards, bulletin, and handbook. Unless otheruise specified, the following specification, standards, bulletin, and handbook of the issue listed in that issue of the Department o

17、f Defense Index of Specifications and Standards specified in the solicitation, form a part of this drauing to the extent specified herein. SPECIFICATIOW MILITARY MIL-1-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS MI L ITARY MIL-STD-883 - Test Methods and Procedure

18、s for Microelectronics. MIL-STD-973 - Configuration Management. MIL-STO-1835 - Microcircuit Case Outlines. - 1/ Stresses above the absolute maxinrm rating may cause permanent damage to the device. maximun levels may degrade performance and affect reliability. - 2/ ALL voltage values referenced to V,

19、. - 3/ Values uill be added when they become available. Extended operation at the Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5762-74642 BULLET IN I- MILITARY STANDARD1 ZED MILITARY DRAWING I DEFENSE ELECTRONICS SUPPLY CENTER MIL-BUL-103 - Li

20、st of Standardized Military Drawings (snOis). HANDBOOK MILITARY MIL-HDBK-780 - Standardized Military Drawings. (Copies of the specification, standards, bulletin, and handbook required by manufacturers in connection with specific acquisition functions should be obtained from the contracting activity

21、or as directed by the contracting activity.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. 3. REQUIREMENTS 3.1 The individual item requirements for device class M shall be in accor

22、dance with 1.2.1 of MIL-STO-883, “Provisions for the use of MIL-STD-883 in conjunction uith compliant non-JAN devices“ and as specified herein. device manufacturers Quality Management (QM) plan, and as specified herein. specified in MIL-STD-883 (see 3.1 herein) for device class M and MIL-1-38535 for

23、 device classes Q and V and herein. Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-1-38535, the 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as 3.2.1 3.2.2 Terminal connec

24、tions. 3.2.3 Block diagram. 3.3 Electrical Derformance characteristics and wstirradiation parameter limits. Case outline(s1. The case outline(s1 shall be in accordance uith 1.2.4 herein and figure 1. The terminal connections shall be as specified on figure 2. The block diagram shall be as specified

25、on figure 3. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating teniperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the

26、 subgroups specified in table II. Marking for device class M shall be in The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked uith the PIN listed in 1.2 herein. accordance with MIL-STD-883 (see 3.1 herein). MIL-BUL-103. In addition, the manufacturer% P

27、IN may also be marked as listed in Marking for device classes Q and V shall be in accordance with MIL-1-38535. 3.5.1 Certification/compliance mark. The conpliance mark for device class M shall be a Vnt as required in MIL-STD-883 (see 3.1 herein). in MIL-1-38535. The certification mark for device cla

28、sses Q and V shall be a WMLot or iiQii as required 3.6 Certificate of compliance. For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-BUL-103 (see 6.7.2 herein). classes Q and V, a certificate of complianc

29、e shall be required from a PML-38535 listed manufacturer in order to supply to the requirements of this drauing (see 6.7.1 herein). The certificate of conpliance submitted to DESC-EC prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets,

30、for device class M, the requirements of MIL-STD-883 (see 3.1 herein), or for device classes Q and V, the requirements of MIL-1-38535 and the requirements herein. For device SIZE 5962-94642 A DAYTON, OHIO 45444 I WISlCN LEVEL I S-EET I I I I 4 DEscFoFM193A Provided by IHSNot for ResaleNo reproduction

31、 or networking permitted without license from IHS-,-,-STANDARD1 SED SI SE MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 ISICNLML 5962-94642 S-EET 5 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-o1 o1 o1 o1 o1 o1 o1 o1 o1 o

32、r o1 o1 o1 o1 0.7 V, 2 2.2 3.5 3.5 3.5 -5 -5 5 -5 STANDARDI ZED SIZE MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 f3EVISIOILML 5962-94642 SET 6 TABLE I. Electrical performance characteristics. Conditions 1/ -55C 5 T, 5 +125C unless otherwise specified Group A subg r oups D

33、evice I Limits Unit Test Max VIH (CMOS) VOUT = 0.1 V or v, - 0.1 v, IIOUTI = 20 ILA V High-level input vol tage, CMOS inputs V High-level input vol tage, TTL inputs VouT = 0.1 V or v, - 0.1 v, = 20 pi, v, = 4.5 v 12.3 V 0.3 V, V Lou- level input vo 1 tage, CMOS inputs VIL (CMOS) Vou, = 0.1 V or v, -

34、 0.1 v, IIOUTI = 20 ILA, Voo = O V or 5.5 V Lou-level input vol tage, TTL inputs 0.8 V V High-level output voltage VOH I, = -2 nui (2 BA output type) i, -6 BA (4 BA output type) I, = -10 Id (8 BA output type) 0.4 V Lou-level output vol tage I, = 2 Inn (2 BA output type) 0.4 I, = 6 nui (4 BA output t

35、ype) 0.4 I, = 10 Inn (8 BA output type) 5 ILA Input leakage current , CHOS/TTL inputs with no pull-up resistors V, = V, or V, -185 ILA High-level input leakage current V, = V, pull-up high res i s t ors 1,283 185 V, = V, pull-down high res i s t ors - 135 Low-level input leakage current VIN r v, pul

36、l-up low resistors I IN table. 135 VIN = V, pull-down low resistors L ;ee footnotes at end Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-74642 E 9999996 0063052 LO4 M v,+ (CMOS) to VTH- ( CMOS V,+ (TTL) to VTH- (TTL) See 4.4.1 Output=hi gh

37、 inpedance, See 4.4.1 TABLE 1. Electrical performance characteristics - continued. 1,2#3 1,2,3 4 4 Test Devi ce type Limits Unit Conditions lJ Group A -55C 5 T, 5 +125“C unless otheruise specified subgroups VOUT = Vss or VDD 1,2,3 1,2,3 IOUT = 0 d, 1,2,3 VI, = V, or V, Vou, = 0.1 V or V, - 0.1 1 ,2,

38、3 v, IIOUTI = 20 KA Min Max Output leakage state outputs current, three- I oz o1 -10 10 KA Output leakage current, open- drain outputs I Out o1 -10 10 KA ai 24 KA Quiescent supply current, no pull- up or pull-doun devices, all valid input combinat ions I DD Threshold voltage, CMOS Schmitt trigger o1

39、 0.4 V, 1 .O3 V, V o1 0.29 VDD 0.76 V, v, - (CMOS ) Vou, = 0.1 V or VDo- 0.1 VI IIOUTI = 20 KA Threshold voltage, TTL Schmitt trigger o1 1.2 2.4 V o1 0.8 2 V Hysteresis voltage, CMOS Schmitt trigger V“, (CMOS 1 o1 0.11 VOO 0.27 V, Hysteresis voltage, TTL Schmitt trigger o1 0.05 VDD 0.14 V, V o1 20.0

40、 PF Input capacitance Output capacitance cDUT o1 25.0 PF o1 30.0 PF I/O capacitance CID Configured as input, See 4.4.1 Functional testing See 4.4.lb I 788 o1 AC electrical characteristics 2J o1 ns See figure 4 v, = 4.5 v CLKl pulse uidth, o1 l3 I ns 9,10,11 9,10,11 9,10,11 high I I l3 CLKl pulse uid

41、th, 1 ou o1 l3 I ns o1 ns Setup time, rising edge of CLK1 RS4 - RSO to I I I !e footnotes at end of table. STANDARD1 ZED 5962-94642 MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-

42、TABLE I. Electrical wrformance characteristics - continued. Conditions I/ Group A Device Limits Unit -55C S T, 5 +125OC subgroups type Test Symbol unless otherwise specified AC electrical characteristics - continued 1/ Setup time, SEL* 5 See figure 4 to rising edge of v, = 4.5 v CLKI Setup time, 6 A

43、DR-LATCH* to rising edge of CLKI Data bus driven 7 from the rising edge of CLKI Time for ACK* 8 asserted from falling edge of CLKI 3J Time taken to 9 negate ACK* from falling edge of CLKl Hold time, 10 before ee footnotes at end CEWTER Provided by IHSNot for ResaleNo reproduction or networking permi

44、tted without license from IHS-,-,-Group A Device Limits subgroups type Min Max Unit Test Conditions IJ -55OC 5 T, 5 +125OC unless otherwise specified SYnbOl Setup time, 82 for HSKI before the rising edge of CLKI See figure 4 v, = 4.5 v IRP* asserted from the rising edge of CLKI I/ HSKI asserted from

45、 the rising edge of CLKI I/ HSKO to rising edge of CLKI Setup time, 84 85 86 HSKI negation from rising edge of CLKI 3/ HSKI asserted from the rising edge of CLKI 3J rising edge of CLKl HSKI negation from 87 88 89 RTS* negated from rising edge of CLKI Setup time, CTS* before rising edge of CLKI 93 94

46、 STANDARD1 SED SI SE MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISICNLML 5962-94642 SEET 14 TABLE 1. Electrical Performance Characteristics - continued. 9,10,11 o1 O Nunber of CLKl clock periods required before IRP* recognized 9, IO, 11 o1 83 o1 9,10,11 9, IO, 11 o1 9

47、, IO, 11 o1 O 9, IO, 11 o1 9,10,11 o1 9,10,11 o1 CLKl periods required from loading HSKCRO to HSKI asserted 9, IO, 11 o1 90 HSKl asserted from rising edge of CLKI 9, IO, 11 o1 RTS* asserted from rising edge of CLKl I/ 9,10,11 o1 9, IO, 11 o1 9, IO, 11 o1 7 Provided by IHSNot for ResaleNo reproductio

48、n or networking permitted without license from IHS-,-,-SMD-5962-9ub42 9999996 00630bO 280 Group A Device subgroups type I I TABLE I. Electrical performance characteristics - continued. Limits Unit Min Max Test I symbl I Conditions I/ -55C d T, d +125“C STANDARD1 ZED MILITARY DRAWING DEFENSE ELECTRON

49、ICS SUPPLY CENTER DAYTON, OHIO 45444 I I unless otheriise specified AC electrical characteristics - continued 2J CTS* after rising edge of CLKl DSR before rising edge of CLKl v, = 4.5 v Setup time, SI 2E 5962-94642 A FWISICNLML SEET 15 Hold time, 97 DSR after rising edge of CLKl DCD* before rising edge of CLKl Setup time, 98