DLA SMD-5962-93105 REV C-1996 MICROCIRCUIT DIGITAL CMOS 32-BIT HIGH INTEGRATION MICROPROCESSOR MONOLITHIC SILICON《硅单片 32位高集成微型处理器 氧化物半导体数字微型电路》.pdf

《DLA SMD-5962-93105 REV C-1996 MICROCIRCUIT DIGITAL CMOS 32-BIT HIGH INTEGRATION MICROPROCESSOR MONOLITHIC SILICON《硅单片 32位高集成微型处理器 氧化物半导体数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-93105 REV C-1996 MICROCIRCUIT DIGITAL CMOS 32-BIT HIGH INTEGRATION MICROPROCESSOR MONOLITHIC SILICON《硅单片 32位高集成微型处理器 氧化物半导体数字微型电路》.pdf（32页珍藏版）》请在麦多课文档分享上搜索。

1、LTR SHEET 15 I 16 17 REV STATUS OF SHEETS A B C 18 I 19 20 21 22 23 24 25 26 27 28 29 30 31 REV cccccccccccccc SHEET 12 3 4 5 6 7 8 9 1011121314 DESCRIPTION SIZE A REVISIONS CAGE CODE 5962-931 05 67268 DATE (YR-MO-DA) Add devices 03, 04. Editorial changes throughout. Add devices 05, 06, 07, 08. Edit

2、orial changes throughout. Add device types 09 and 10. Update boilerplate. 94-03-23 96-03-28 96-10-28 APPROVED Monica L. Poelking Monica L. Poelking Monica L. Poelking PMIC NIA STANDARD MICROC IRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENS

3、E AMSC NIA PREPARED BY Thomas M. Hess DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 4321-5000 CHECKED BY Thomas M. Hess MICROCIRCUIT, DIGITAL, CMOS, 32-BIT HIGH INTEGRATION MICROPROCESSOR, MONOLITHIC SILICON APPROVED BY Monica L. Poelking DRAWING APPROVAL DATE 93-02-26 REVISION LEVEL C SHEET 1 OF 31

4、 DESC FORM 193 JUL 94 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 5962-E003-97 SUD-5962-93105 REV C = 9999996 0090533 TTL Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-1. SCOPE 1.1 m. This drawing documents thr

5、ee product assurance class levels consisting of space application (device classe a), high reliability (device classes M and a), and non traditional performance enviroment (device class NI. A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Nunber (

6、PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. For device class N, the user is cautioned to assure that the device is appropriate for the application envirornment. 1.2 m. The PIN is as shown in the following example: 93105 I f Federal RHA Device

7、 Devi ce Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) 11 u- (see 1.2.3) / Drawing nhr 1.2.1 MA des- . Device classes Y, P and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the a

8、ppropriate RHA designator. specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A A dash (-) indicates a non-RHA device. 1.2.2 Device tem . The device typeCs) identify the circuit function as follows: Devi ce twe

9、Generic numbe r Device types 03 and 04 provide testability features compatible with the IEEE Standard Test Access Port and Boundry Scan Architecture (IEEE Standard 1149.1). system management enhancement (SL). 2/ Any device outside the traditional performance environment; e.g., an operating temperatu

10、re rangefor device types 01-08 -55C to +125“C and device types 09 and 10 -40C to +llO“C and which requires hermetic packaging. Device type 05, 06, 07, 08, 09 and 10 are JTAG compatible and have the I SIZE STAN DARD A 5962-931 05 I MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS REVISION LEVEL SH

11、EET I C 2 COLUMBUS, OHIO 43216-5000 80486DX-25 80486DX-33 80486DX2-50 80486DX2-66 80486DX-25 80486DX-33 80486DX2-50 80486DX2-66 80486DX2-50 80486DX2-66 32 Bit High Integration Microprocessor 32 Bit High Integration Microprocessor 32 Bit High Integration Microprocessor 32 Bit High Integration Micropr

12、ocessor 32 Bit High Integration Microprocessor 32 Bit High Integration Microprocessor 32 Bit High Integration Microprocessor 32 Bit High Integration Microprocessor 32 Bit High Integration Microprocessor 32 Bit High Integration Microprocessor 1.2.3 Device class designator . The device class designato

13、r is a single letter identifying the product assurance level as follows: Device class Device rwuirements documentation M N Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Certification and quali

14、fication to MIL-PRF-38535 with nontraditional performance environment 2/ a or v Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(G . The case outline(s) are as designated in MIL-CTD-1835 and as follows: Outline letter Descr i Dt ive desi anatoc Terminals v I X Y CMGA9- P168 See Fi

15、gure 1 168 196 Ceramic, pin grid array Leaded chip carrier with DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-73305 REV C W b 0090535 874 W SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS REVISION

16、LEVEL C COLUMBUS, OHIO 43216-5000 1.3 Absolutem ratir(gs -2/ Storage temperature range -65C to +150“C Supply voltage with respect to ground range . -0.5V dc to +6.5V dc Voltage on any pin with respect to ground range . -0.5V dc to +5.5V dc Maximum power dissipation (PD) Device O1 and 05 . 3.675 U De

17、vice 02 and 06 . 4.725 U Device 03, 07, 09 . 4.988 U Device 04, 08, 10 . 6.3 U Lead temperature (soldering, 10 seconds) 300C Thermal resistance, junction-to-case (JC): CaseX 1.5“C/U CaseY 2.5“C/U Maximum junction temperature (TJ) Devices 01,02,05,06: Case X Devices 03,04,07,08: Case X Devices 09 and

18、 IO: Case X (TJ) = 119C; Case Y (TJ) = 125.8“C (TJ) = 132.1“C; Case Y (TJ) = 134.5“C; Case Y (TJ) = 136.8“C (TJ) = 140.8“C 1.4 -. Case operating temperature range (TC) 01-08 . Case operating temperature range (TC) 09-10 . Supply vol tage, (VCC) -55C to +125“C -40C to +11o“C 4.75 V dc i Vcc i 5.25 V

19、dc 1.5 pisita 1 loaic t estins for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) . 98.5 percent 2. APPLICABLE DOCUMENTS 2.1 Government swc ification. standards. and handbooks. The following specification, standards, and handbooks form

20、 i part of this drawing to the extent specified herein. those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. Unless otherwise specified, the issues of these documents are 5962-931 05 SHEET 3 SPECIFICA

21、TION MILITARY MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. STANDARDS MILITARY MIL-STD-883 - Test Methods and Procedures for Microelectronics. MIL-STD-973 - Configuration Management. MIL-STD-1835 - Microcircuit Case Outlines. HANDBOOKS MILITARY MIL-HDBK-103 - List of

22、 Standard Microcircuit Drawings (SMDIS). MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the jtandardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) !.2 No

23、n Government oublications . ierein. if the DODISS cited in the solicitation. ire the issues of the docwnts cited in the solicitation. The following document(s) for a part of this document to the extent specified Unless otherwise specified, the issues of the documents which are DOD adopted are those

24、listed in the issue Unless otherwise specified, the issues of docunents not listed in the DODISS Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-93105 REV C m 9999996 0090536 700 m REVISION LEVEL C INSTITUTE OF ELECTRICAL AND ELECTRONICS ENG

25、INEERS (IEEE) IEEE Standard 1149.1 - IEEE Standard Test Access Port and Boundary Scan Architecture. (Applications for copies should be addressed to the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, Piscataway, NJ 08854-4150. ) (Non-Govermnt standards and other publications are no

26、rmally available from the organizations that prepare or distribute the documents. sevices.) These docunents may also be available in or through libraries or other informational 2.3 Order of Drecedence. In the event of a conflict between the text of this drawing and the references cited herein, the t

27、ext of this drawing takes precedence. regulations unless a specific exemption has been obtained. Nothing in this document, however, supersedes applicable laws and 3. REQUIREMENTS 3.1 Jtem reauir- . The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535

28、and as specified herein or as modified in the device manufacturerls Quality Management (QM) plan. modification in the QM plan shall not affect the form, fit, or function as described herein. requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level

29、 B devices and as specified herein. The The individual item 3.2 Desisn. con struct ion. and D hvsical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes N,Q and V or MIL-PRF-38535, appendix A and herein for device class

30、M. 3.2.1 Case outlinetsr . The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. SHEET 4 3.2.2 Jerminal connections . 3.2.3 Block d iaarai. The terminal connections shall be as specified on figure 2. The block diagram shall be as specified on figure 3. I 3.2.4 -Y Scan Instructio

31、n Codea a For device 03 - 10 the boundary scan instruction codes shall be as specified on figure 4. I 3.2.5 Jimins waveform . 3.2.6 bdiation exposu re ci rcuit. The timing waveforms shall be as specified on figure 5. The radiation exposure circuit shall be as specified when available. I 3.3 Flectr i

32、cal Derformance characteristics and ws tirradiation Darameter 1 imits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test re

33、auir- . The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 m. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturerls PIN may also be marked as listed in MIL-HDBK-103. t

34、o space limitations, the manufacturer has the option of not marking the 115962-11 on the device. this option, the RHA designator shall still be marked. with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. For packages where marking of the entire SMD P

35、IN nuniber is not feasible due For RHA product using Marking for device classes N,Q and V shall be in accordance 3.5.1 Cert ification/c omrliance mark . The certification mark for device classes N,Q and V shall be a llQMLtl or liQi1 as required in MIL-PRF-38535. appendix A. The compliance mark for d

36、evice class M shall be a llC1l as required in MIL-PRF-38535, . 3.6 Certificate of cmliance For device classes N, Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). class M, a certifica

37、te of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). an approved source of supply for this drawing shall affirm that the manufacturerls product meets, for device classes N,Q and V, the requirements of MIL-PRF

38、-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. For device The certificate of compliance submitted to DSCC-V

39、A prior to Listing as ancg. A certificate of conformance as required for device classes N, Q and V in I 3-7 Certificate Of conform STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 5962-931 05 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or

40、networking permitted without license from IHS-,-,-SMD-5962-93305 REV C 9999996 0090537 647 Devi ce type Test Limits Unit Min I Max Input low voltage Symbol Input high voltage Group A Conditions 1/ subgroups 4.75 V i Vcc 5 5.25 V unless otherwise specified Output low voltage z/ $.J VIL “IH VOL Output

41、 high voltage u Frequency = 8 MHz u 3 Il2,3 Frequency = 8 MHz 3/ 1 #2,3 IOL = 4.0 mA 1,2,3 IOL = 5.0 mA Input leakage current 10 01,03, 05.07 input leakage current 2.4 V Input leakage current Icc Output leakage current Vcc Vcc MAX Supply current 04,08 10 o1 ,oz, 05,07, 99 03,04, 06.08. CLK input cap

42、acitance 09- 1200 20 PF 15 Input capacitance SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS REVISION LEVEL C COLUMBUS, OHIO 43216-5000 TABLE I. Electrical Derfo rmance characteristics. 5962-931 05 SHEET 5 ILI 1 VIN = GND and VCC 1.2.3 Frequency = 1 MHz See 4.4.l.c CCLK I Frequen

43、cy = 1 MHz See 4.4.l.c 4 1- 06.08. All I -15 I +I5 I 01.05-700 mA 02.06 900 03,07 I 1 950 1 06.08, See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SflD-5962-93L05 REV C 9999996 00905L8 583 Conditions r/ 4.75 V s Vcc I 5

44、.25 V unless otherwise specified subgroups type - Min Frequency = 1 MHz See 4.4.l.c See 4.4.l.b 01,02, 4 Q5.07.09 03,04, 06.08.10 7.8 ALL 125 125 ns System clock period s/ t 1 9,10,11 9,10,11 01,03,05,07 14 09- 02,04,06,08 11 10 01,03,05,07 14 09- 02,04,06,08 11 System clock fall time e/ t4 2.0 V to

45、 0.8 V See figure 5 9,10,11 01,03,05,07 09 02,04,06,08 10 A2-A31 ,PUT ,PCD ,BEO-3#,M/IO#, D/C#,U/R#,ADS#,LOCK#, FERR#,BREP,HLDA VALID DELAY A2-A31,PUT,PCD,BEO-3#,M/IO#, D/C#,U/R#,ADS#,LOCK# FLOAT DELAY t6 t7 9,10,11 O1 2 02, 2 03,05,07,09 2 04,06,08,10 2 9,10,11 O1 02, 03,05,07,09 04,06,08,10 27 22

46、24 ns See figure 5 9,10,11 O1 2 02, 2 03,05,07,09 2 04.06.08.10 2 TABLE I. FLectrical oerfor mance character isticg. I Group A IDevice Unit Test Max 4- I Input/output capacitance See figure 5 I at 2.0 V See figure 5 System clock high time 2 ns I t3 System clock low time at 0.8 V See figure 5 4 1 ns

47、I 0.8 V to 2.0 V See figure 5 -1 4 ns 3 I t5 System clock rise time e/ 02,04,06,08 See figure 5 See figure 5 28 20 PCHK# VALID DELAY I See footnotes at end of table. 5962-931 05 STAN DARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 I SHEET 6 REVISION LEVEL C DECC FO

48、RM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SflD-5962-93IiO5 REV C 9999996 0090539 43T W t8a See figure 5 t9 t10 tll See figure 5 See figure 5 See figure 5 t12 See figure 5 t13 See figure 5 ti4 t15 See figure 5 See figure 5 tl6 See

49、 figure 5 SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS REVISION LEVEL C COLUMBUS, OHIO 43216-5000 5962-931 05 SHEET 7 TABLE 1. Electrical Derfnrrnance characterist ics. Test Group A subgroups Devi ce type Unit Limits Symbol Conditions 1/ 4.75 V L Vcc ect ion for device classes N. Q and y . Qualification inspection for device classes N, Q and V shall be in accordance with MIL-PRF-38535. and herein for groups A, 6, C, D, and