DLA SMD-5962-88506-1988 MICROCIRCUITS N-CHANNEL MOS MULTIFUNCTION PERIPHERAL MONOLITHIC SILICON《硅单片N通道MOS多功能周边微电路》.pdf

《DLA SMD-5962-88506-1988 MICROCIRCUITS N-CHANNEL MOS MULTIFUNCTION PERIPHERAL MONOLITHIC SILICON《硅单片N通道MOS多功能周边微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-88506-1988 MICROCIRCUITS N-CHANNEL MOS MULTIFUNCTION PERIPHERAL MONOLITHIC SILICON《硅单片N通道MOS多功能周边微电路》.pdf（27页珍藏版）》请在麦多课文档分享上搜索。

1、REVISIONS LTR DESCRIPTION I DESC-DWG-8850b 57 0 7797775 0011798 7 - DISTRIBUTION STATEMENT A. Approved for public release; distribution Is unlimited. 1 /- I - -7 _ _ PMIC N/A STANDARDIZED MILITARY DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPAmEMS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMS

2、C NIA I I SHEET 1 OF 27 I PREPAREDBY 1 DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 MICROCIRCUITS, N-CHANNEL MOS MULTIFUNCTION PERIPHERAL, MONOLITHIC SILICGN 59 6 2-8 8506 SIZE CAGE CODE A 67268 25 APRIL 1988 I RVSINLEVEL t I . DESC FORM 193 SEP 87 U.S. GOVfRWNT PRINTING OFFICE: 1987 - 748-1

3、2916091 1 5962- E693 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-r SIZE A STANDARDIZED 1. SCOPE 5962-88506 1.1 SCO e. This drawing describes device requirements for clas? El microcircuit? in accordance rith 1.7.0 V dc -65C to +150 C 1.5 +270 C +1

4、70C See MIL-M-38510, appendix C Recommended operating conditions. Supply vol tage: VCC-“ vss-“ High level input voltage (logic inputsI(V1 1 - - - - - Low level input voltage (logic inputs)(VIL r - - - - - - Minimum high level output voltage - - - - - - - - - - - Maximum low level output voltage - -

5、- - - - - - - - - Frequency of operation: Case operating temperature range (TC) - - - - - - - - - Devicetype01 _-_- Device type 02 - - - - - - - - - I - - - - - - - - - 4.75 V dc to 5.25 V dc ov 2.0 v to vc GND to 0.8 dc 2.4 V dc 0.5 V dc 1.0 to 4.0 MHz 1.0 to 5.0 MHz -55C to +125C Provided by IHSNo

6、t for ResaleNo reproduction or networking permitted without license from IHS-,-,-ind as specified herein. SIZE A STANDARMZED 3.2 Design, construction, and physical dimensions. The design, construction, and physical iimensions shall be as specified in MIL-M-38510 and herein. 5962-88506 3.2.1 Case out

7、lines. The case outlines shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagram. The block diagram shall be as specified on figure 2 3.3 Electrical performance characteri stics. Unless otherwise specified,

8、 the electrical ierformance characteristics are as specified in table I and apply over the full recommended case sperati ng temperature range. 2. APPLICABLE DOCUMENTS 2.1 .Government specification and standard. Unless otherwise specified, the following ipecification and standard, of the issue listed

9、 in that issue of the Department of Defense Index of ;pecifications and Standards specified in the solicitation, form a part of this drawing to the !xtent specified herein. SPECIFICATION MILITARY I4 IL -M- 385 10 - Microcircuits, General Specification for. STAN DARD MILITARY MI L-STD-883 - Test Meth

10、ods and Procedures for Microelectronics. (Copies of the specification and standard required by manufacturers in connection with specific icquisition functions should be obtained from the contracting activity or as directed by the :ontracting activity. 1 *eferences cited herein, the text of this draw

11、ing shall take precedence. 2.2 Order of precedence. 3. REQUIREMENTS 3.1 In the event of a conflict between the text of this drawing and the Item requirements. The individual item requirements shall be in accordance with 1.2.1 of IIL-STD-883. “Provisions for the use of MIL-STD-883 in conjunction with

12、 compliant non-JAN devices“ DESC-DWG-85b 57 0 9977775 OOLZOOO T E I DESC FORM 193A U S GOVERNMENT PRINTING OFFICE 1987-549096 SEP 87 / P /y 3 3.4 Marking. Marking shall be in accordance with MIL-STD-883 (see 3.1 herein). The part shal In addition, the manufacturers part number be marked with the par

13、t number listed in 1.2 herein. nay also be marked as listed in 6.5 herein. 3.5 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in 6.5. The certificate of compliance submitted to DESC-ECS prior to listi

14、ng as an approved source of supply shall state that the nanufacturers product meets the requirements of MIL-STD-883 (see 3.1 herein) and the requirements herein. 3.6 Certificate of conformance. A certificate of conformance as required in MIL-STD-883 (see 3.1 herein) shall be provided with each lot o

15、f microcirulits delivered to this drawing. 3.7 Notification of change. Notification of change to DESC-ECS shall be required in accordance with MIL-STD-883 ( see 3.1 herein). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TABLE , El ectrical performa

16、nce characteristics. Test i Symbol I I VOL I Power supply current I Icc outputs open Low level out ut voltage (except tilTA&) Hi h level output voltage IVOH I Qexcept TIXK) DTXR output source current IOH I I I IOL I DTACR output sink current Input leakage current IIIM I Three-state output current I

17、ILOH Three-state output current / ILOL in float I in float I Hi h level input voltage /VIH I !ail inputs) Low 1 eve1 input vol tage )VIL (all inputs) I Input capacitance ICIN I Three-state output I COUT Functional tests I I See footnotes at end of table capacitance Conditions unlesibotherwise specif

18、ied VCC = 5.25 V VOUT = 2.4 V VIN I O to 5.25 V See 4.3.1 See 4.3.1 See 4.3.ld I I roup A 1 Limits iUnit iubgroups I I I I Min I Max I I I I I 1,2,3 I I 180 I mA 7- I I 1,2,3 1 I 0.5 I V I I I 1,2,3 I 2.4 V I I I I 1,2,3 I I I I 1-40 I DA I I I I I I I I 1,2,3 I I 5.3 I mA I I I I I I 1,2,3 I -10 I

19、+lo I NA 1 1,2,3 I I +lo I NA 1,2,3 I I -10 I UA : I I I I I I 1,2,3 1 2.0 I 1,2,3 i -0.3 i 0.8 i V 41 I 10 I pF I I I I I I I 10 I pF 1 I 41 I i I I I 7,8 I I I SIZE A STANDARDIZED MILITARY DRAWING 59- DEFENSE UECTRONICS SUPPLY CENTER RMWN LEVEL SHEET DAYCON, OHD 45444 4 #? U S. GOVERNMENTPRHTING O

20、FFICE. 1887-549088 ESC FORM 193A SEP 87 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- DESC-DWG-BB506 59 = 7777775 OOL2002 3 I I TABLE I. Electrical performance characteristics - Continued. I Test STANDARDIZED SIZE A I I I I I I 5962-88506 ISymbol

21、I Conditions I/ IRefer-I Group A I Limi ts IUni t I I -55C assed to the processor must be located in the low byte of the data word. As a result, DO-D7 of the XFP must be connected to the low order eight bits of the processor data bus, placing CMFP registers at odd addresses if vectored interrupts ar

22、e to be used. These signals generate interrupts at the same priority Timer outputs (TAO, TBO, TCO, and TDO). This output signal may be used to supply the universal synchronous/asynchronous During an interrupt However, during an interrupt acknowledge cycle, the vector number STANDARMZED SIZE MILITARY

23、 DRAWING A 5962-88506 DEFENSE ELECTRONICS SUPPLY CENTER RMSION LEVEL SHEET DAMON, OHIO 45444 25 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-I. . SIZE A STANDARDIZED Reset (RESEf). This input will initialize the CMFP during power-up or in response

24、 to a total Interrupt control, The interrupt request and interrupt acknowledge signal s are handshake 1 ines system reset, For a vectored interrupt scheme. Interrupt enable in and the interrupt enable out implement a dai cy-c hai ned i nterrupt structure, Interrupt Request (m). This output signals t

25、he processor that an interrupt is pending from the :MFP. These are 16 interrupt channels that can generate an interrupt request. Clearing the Interrupt pending registers (IPRA and IPRB) or clearing the interrupt mask registers (IMRA and IMRB) Mill cause TlQ to be negated, :ycle, unless additional in

26、terrupts are pending in the CMFP. icknowledge cycle when IACK and DS are asserted. The CMFP will supply a unique vector number to the Jrocessor which corres onds to the interrupt handler for the particular channel requiring interru t service. interrupt structure for a vectored interrupt scheme, is r

27、equesting interrupt service. So, the highest priority device in the chain should have its pin tied low, allowed to pass a vector number to the processor until its !T pin Lasserted. daisy-chain option is not implemented, all CMFPs should have their IEI pin tied low. The full duplex serial channel is

28、implemented by a serial input and output line. The Independent receive and transmit sections may be clocked by separate timing signals on the receiver clock input and the transmitter clock input. Serial Input (SI), This input line is the USART receiver data input, This input is not used in the USART

29、 loopback mode. Serial Output (SO), This output line is the USART transmitter data output. This output is driven high during a device reset, Receiver Clock (RC), This input controls the serial bit rate of the receiver. This signal may be supplied by the timer output lines or by any external TTL-leve

30、l clock which meets the minimum and maximum cycle times. This clock is not used in the USART loopback mode. will also be negated as the result of an interrupt acknowledge and TET are active, the CMFP will begin an interrupt Interrupt Acknowledge - (m), If both In a daisy-c f: ained interrupt structu

31、re, all devices in the chain must have a common d. Interrupt Enable In (MI. This input, together with the signal, provides a daisy-chained indicates that no higher priority device During an interrupt acknowledge cycle, an CMFP with a pending interrupt is not When the Serial I/O control. 5962-aa506 T

32、ransmitter C may be supplied and maximum cyc Df44 control, status 1 i nec, MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 ock (TC), This input controls the serial bit rate of the transmitter. This signal by the timer output lines or by an external TTL-level clock which meets t

33、he minimum e times, The USART supports DMA transfers through its receiver ready and transmitter ready REVISION LEVEL SHEI 26 Receiver Ready (RR). This output reflects the receiver buffer full status for DMA operations, Transmitter Ready (m). This output reflects the transmitter buffer empty status f

34、or DM ope rat ions. IESC FORM 193A SEP 87 -_- _-e- I_ 7 - * US. QWERNMENT PRLNTING OFFICE: 1987-548098 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-i. 1 DESC-DWG-BB5Ob 59 W 9999795 001202q 2 = 6.5 Approved source of supply. An approved source of s

35、upply is listed herein. Additional jources will be added as they become available. The vendor listed herein has agreed to this drawing ind a certificate of compliance (see 3.5 herein) has been submitted to DESC-ECS. I I Vendor I Vendor I Rep1 acement r I Military drawing I CAGE I similar part milita

36、ry specification1 I part number I number I number L/ I part number I l I l I I l I I I I 5962-8850601XX I 50088 I TS68901MCB/C4 I I I I I I 5962-8850601YX I 50088 I TS68901MEB/C4 I I I I I I I I I I 5962-8850602XX I 50088 I TS68901MCB/C5 I I 5962-8850602YX I 50088 I TS68901MEB/C5 I I I I I - - - i/

37、Caution. Do not use this number for item acquisition. Items acquired to . thismber may not satisfy the performance requirements of this drawing. Vendor CAGE number 50088 Vendor name and address Thomson-Components-Mostek Corporation P.O. Box 169 1310 Electronics Drive Carro1 1 ton, TX 75006 STANDARMZED SIZE A 5962-88506 MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CEMER RMSDN LEVU SHEET DAYTON, OHIO 45444 27 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-