DLA SMD-5962-86811-1991 MICROCIRCUITS EXTENDED DUAL CHANNEL DIRECT MEMORY ACCESS CONTROLLER MONOLITHIC SILICON《硅单块 扩展双沟道直接存储器存取 微型电路》.pdf

《DLA SMD-5962-86811-1991 MICROCIRCUITS EXTENDED DUAL CHANNEL DIRECT MEMORY ACCESS CONTROLLER MONOLITHIC SILICON《硅单块 扩展双沟道直接存储器存取 微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-86811-1991 MICROCIRCUITS EXTENDED DUAL CHANNEL DIRECT MEMORY ACCESS CONTROLLER MONOLITHIC SILICON《硅单块 扩展双沟道直接存储器存取 微型电路》.pdf（33页珍藏版）》请在麦多课文档分享上搜索。

1、SMD-59b2-bLL 59 = 9999996 0003225 3 = .- I REV STATUS OF SHEETS PMIC PUA STANDARDIZED MILITARY DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARtMEMS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC NIA DESC FORM 193 SEP 87 DEFENSE ELECTRolrllcs SUPPLY CENTER DAYTON, Wi 45444 DRAW IN APPROVAL DAT

2、E SIZE MECODE 26 FEB 91 A 67268 5962-86811 REVISION LEVU. SHEET 1 OF 32 DISTRIBUTION STATEMENT A. Approved for public release; distribution Is unlimited. U.S. GOVERNMEHI PRIHIHKI o(ftC: 1987 - 7411-1291609l1 5962-El 557 Provided by IHSNot for ResaleNo reproduction or networking permitted without lic

3、ense from IHS-,-,-, $ *A SMD-59b2-8bBlL 59 = 9999996 0003226 5 1. SCOPE 1.1 SCO e. This drawinglldescribes device requirements for class B microcircuits in accordance with 1.7-ff MIL-STD-883, non-JAN devices“. 1.2 Part or Identifying Number (PIN). exampl e: Provisions for the use of MIL-STD-883 in c

4、onjunction with compliant The complete PIN shall be as shown in the following 5962-86811 1 I I i Drawing number “f I I I Device t pe ( 1.2.11 T I I I Case outline (1.2.2) X I I I I Lead finish per MI L-M- 38510 1 1.2.1 Device type(s). The device types) shall identify the circuit function as follows:

5、 Device type Generic number I Circuit function o1 68442-8 Extended dual channel direct memory access control ler I 1.2.2 Case outline(s1. The case outline(s) shall be as designated in appendix C of MIL-M-38510 and as follows: I Out1 i ne 1 etter Case outline I X Y 68-pin (1.07“ x 1.07“ x 0.102“), pi

6、n grid array (see figure 1) 68-pin (0.96“ x 0.96“ x 0.125“), ceramic chip, leaded chip carrier package (see figure 2) 1 1.3 Absolute maximum ratings. Supply voltage range with respect to GND (Vcc) - - - - - Storage temperature range - - - - - - - - - - - - - - - Maximum power dissipation - - - - - -

7、 - - - - - - - - - Maximum operating temperature (TC) - - - - - - - - - - - Lead temperature (soldering, 5 seconds) - - - - - - - - Junction temperature (TJ) - - - - - - - - - - - - - - - Thermal resistance, junction-to-case (jc) : Input capacitance (CINI Cases X and y - - - - - - - - - - - - - - -

8、- - - - - - - - - - - - - - - - - - - - - I 1.4 Recommended operating conditions. -0.3 V dC to +7.0 V dC -65C to +150“C 1.75 W -55C to +llO“C +270“C +150“C lO“C/W 13 pF Supply voltage (VCC) - - - - - - - - - - - - - - - - - - High level input voltage (VI Low level input voltage (VIL7 - - - - - - - -

9、 - - - - - Minimum high level output voltage (VO ) - - - - - - - - Maximum low level output voltage VOL - - - - - - - - - Frequency of operation: Device type 01 - - - - - - - - - - - - - - - - - - - - Case operating temperature (TC)- - - - - - - - - - - - - 4.5 V dc to 5.5 V dc GND -0.3 V to 0.8 V 2

10、.4 V dc 0.4 V dc 2.0 to 8.0 MHz -55C to +llOC - - - - - - - - - - - - - 2.0 V dc to Vcc . SIZE A 5962-86811 STANDARDIZED MILITARY DRAWING amstoN LEVEL DEFENSE ELEcTRoE(ICS SUPPLY CENTER SHEET 2 RAMON, OHIO 45444 v .) U. 8. QOVCRNMLNT CRINTINQ OCPICC IOOO-S49-Z49 DESC FORM 193A SEP 87 Provided by IHS

11、Not for ResaleNo reproduction or networking permitted without license from IHS-,-,- SMD-5962-bll 59 W 9999996 0003227 7 = 4- SIZE A STANDARDIZED I -_ I. 2. APPLICABLE DOCUMENTS 5962-86811 2.1 Government specification, standard, and bulletin. Unless otherwise specified, the following ipecification, s

12、tandard, and bulletin of the issue listed in that issue of the Department of Defense Index-of Specifications and Standards specified in the solicitation, form a part of this drawing to ;he extent specified herein. SPECIFICATION - MIL I TARY MIL-M-38510 - Microcircuits, General Specification for. STA

13、NDARD MILITARY MIL -STD-883 - Test Methods and Procedures for Microelectronics. BULLETIN MILITARY MI L-BUL- 103 - List of Standardized Military Drawings (SMDs). (Copies of the specification, standard, and bulletin required by manufacturers in connection with ipecific acquisition functions should be

14、obtained from the contracting activity or as directed by ;he contracting activity.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the -eferences cited herein, the text of this drawing shall take precedence. 3. REQUIREMENTS 3.1 11 L -STD- ind as s8p%fied her

15、ein. Item requirements. The individual item requirements shall be in accordance with 1.2.1 of “Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices“ 3.2 Design, construction, and physical dimensions. The design, construction, and physical limensions shall be as specifi

16、ed in MIL-M-38510 and herein. 3.2.1 Case outline(s). The 3.2.2 Termi na1 connections. 3.2.3 Block diagram. The b case outline(s) shall be in accordance with 1.2.2 herein. The terminal connections shall be as specified on figures 3 and 4. ock diagram shall be as specified on figure 5. 3.3 Electrical

17、performance characteristics. Unless otherwise specified herein, the electrical jerformance characteristics are as specified in table I and shall apply over the full case operating Lemperature range. 3.4 Electrical test requirements. 3.5 Markin . The electrical test requirements shall be the subgroup

18、s ipecified in table IL; The electrical tests for each subgroup are described in table 1. ,e marke d w t the PIN listed in 1.2 herein. IS listed in MIL-BUL-103 (see 6.7 herein). Marking shall be in accordance with MIL-STD-883 (see 3.1 herein). The part shall In addition, the manufacturers PIN may al

19、so be marked m “ U.S. CIOVEANMENT PAINTINQ OFFICE: 1990750527fl )ESC FORM 193A SEP 87 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-8bBLL 59 999999b 0003228 9 tS TABLE I. Electrical performance characteristics. I I 7- 1- I Conditions I -55

20、C J cn n FIGURE 5. Block diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-bLL 59 m 9999996 0003243 5 m STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CEMER NOTE: SIZE A 5962-86811 I REVISONLEVU. I SHEET 0.8 2.0 V Y Timing m

21、easurements are referenced to and from a low voltage to 0.8 Y and a high of 0.2 V, unless otherwise noted. through the range such that the rise or fall wily be linear between 0.8 V and 2.0 V. The voltage swing throu h this range should start outside and pass FIGURE 6. Clock input timing diagram. I I

22、 I 19 RAYTON, OHIO 4!5444 t US. GOMANMENT PRINTINQ OFFICE l90.750527fl IESC FORM 193A SEP 87 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5762-BblL 59 7999996 0003244 7 I SIZE MILITARY DRAWING L A 5962-86811 STANDARDIZED DEFENSE ELECTRONICS SU

23、PPLY CENTER REVISON LEVEL SHEET b 20 DAYTON, OHIO 45444 These waveforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are not intended as a functional description of the input and output signals. Refer to other functional descriptions and thei

24、r related diagrams for device A8/DO .- DBEN NOTE: Timing measurements are referenced to and from a low voltage to 0.8 V and a high of 2.0 V, unless otherwise noted. through the range such that the rise or fall will be linear between 0.8 V and 2.0 V. The voltage swing through this range should start

25、outside and pass FIGURE 7. Waveforms - MPU write cycle timing diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59bZ-bI11 59 m 999999b 0003245 9 m STANDARDIZED MILiTARY DRAWING DEFENSE ELECTRONKZS SUPPLY CENTER RAYTON, OHIO 45444 These wav

26、eforms should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are not intended as a functional description of the input and output signals. operation. Refer to other functional descriptions and their related diagrams for device SIZE A 5962-86811 RMSK)N

27、 LEVEL SHEET 21 I l I R!W - UDCiAO - LDSB - DDlfi - DBEN 31 D write or The value placed on Chi p select (CS) : This input signal is used to select the DDMA for an MPU bus cycle. When CS is asserted, the address on Al-A7 and the data strobes (or Acwhen using an 8-bit bus) select the internal DDMA reg

28、ister that will be involved in the transfer. with the address and data strobes. CS should be generated by qualifying an address decode signal Address strobe (As): This bidirectional signal is used as an output in the DMA mode to indicate that a valid address is present on the address bus. DDMA can t

29、ake control of the bus (if the DDMA has requested and been granted use of the bus). Read/wri te ( R/W) : This bidirectional signal is used to indicate the direction of a data during a bus cycle. In the MPU mode, a high level indicates that a transfer is from the DDMA to the data bus and a low level

30、indicates a transfer from the data bus to the DDMA. transfer from the data bus to the DDMA. address memory or device to the data bus, and low level indicates a transfer from the addressed memory or device to the data bus, and low level indicates a transfer from memory or device. In the MPU or IDLE m

31、odes, it is used as an input to determine when the In the DMA mode, a high level indicates a In the DMA mode? a high level indicates a transfer from the Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SND-57bZ-BbBlL 57 777977b 0003254 T r. J Upper an

32、d lower data strobe (UDS/AO and l3!7/os): These bidirectional lines are used for different purposes depending on whether the DDMA is o erating on an 8-bit or a 16-bit bus. When using a 16-bit bus, these pins functions as UDS and A. - During any bus cycle, u6s is asserted if data is to be transferred

33、 over data lines D8-Dl5 and LDS is asserted if data fs to be transferred over data lines DO-D7. m/LDS are asserted by the DDMA when operating in the DMA mode and by another bus master when in the MPU mode. When using an 8-bit bus, these pins functions as AO and DS. AO is an extension to the lower ad

34、dress lines to provide the address of a byte in the 16 megabyte address map and is valid data is on the bus during a write cycle. Data transfer acknowledge (m This bidirectional line is used to signal that an asynchronous bus cycle may be terminated. MPU mode, this output indicates that the DDMA has

35、 accepted data from the MPU or placed data on the bus for the MPU. a bus cycle. As long asm remains negated, the DDMA will insert wait cycles into a bus cycle and when DTACK is asserted, the bus cycle will be terminated (except when PCL is used as a ready signal, in which case both signals must be a

36、sserted before the cycle is terminated). In the In the DMA mode, this input is monitored by the DDMA to determine when to terminate Bus exception control (Wrrrr through BEIZ): These input line provide as encoded signal that indicates an abnormal bus condition such as a bus error or reset. This outpu

37、t indicates that the DDMA is controlling the bus. on the external address latch drivers and control signal buffers. Upper address ctrobe(m1: This output is used as the gates signal to the transparent latches that capture the value of A8-A23 on the mulitplexed address/data bus. Data buffer enable (BB

38、ER): This output is used as the enable signal to the external bidirectional data buffers. Data direction (DDIR): Phis output controls the direction of the external bidirectional data buffers. data transfer is from the DDMA to the data bus. bus to the DDMA. It is used as the enable signal to turn - I

39、f ObnT is high, the If I)IR is low, the data transfer is from the data lHi gh byte ( HIBYTE) : Th i If wi 1 bus s bidlrectional signal determines the size of the bus used by the DDMA during a reset operation. - this signal is asserted (tied to ground) durin reset, the data bus size is eight bits and

40、 HIBYTE 1 not be used as an output. If it is ne ated fpulled high by a resistor) during reset, the data I size is assumed to be 16 bits and d will be used as an output during single-address DMA transfer between an 8-bit device and a 16-bit memory. As an output, HIBYTE indicates that data will be pre

41、sent on data lines D8-Dl5 that must be transferred to data lines DO-D7 or vice versa through an external buffer during a single address transfer between an 8-bit device and a 16-bit memory. This output is asserted by the DDMA to request control of the bus. * US. GOVERNMENT PRINTING OFflCE: 19907E4-527R DESC FORM 193A SEP 87 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-