DLA SMD-5962-86015 REV C-2011 MICROCIRCUIT DIGITAL CMOS MEMORY 64K X 1 STATIC RAM MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add five vendors, CAGE 61772, CAGE 04713, CAGE 60991, CAGE 50088, and CAGE 65786. Add 04 new device types. Add case outline letter Y. 88-06-17 Michael A. Frye B Boilerplate update, part of 5 year review. ksr 05-09-29 Raymond Monnin C Updated body

2、 of drawing to reflect current requirements. - glg 11-01-05 Charles Saffle CURRENT CAGE CODE 67268 THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED REV SHEET REV C C C C C C C SHEET 15 16 17 18 19 20 21 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 1

3、3 14 PMIC N/A PREPARED BY Rick Officer DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Raymond Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael A. Frye MICROCIRCUIT, DIGITAL, CMOS, MEMORY, 64K X 1, STATIC

4、RAM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 24 June 1986 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 14933 5962-86015 SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E038-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

5、IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86015 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-

6、PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-86015 01 X A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as foll

7、ows: Device type Generic number Circuit Acess time 01 see 6.6 64K x 1-bit, SRAM, TS 35 ns 02 see 6.6 64K x 1-bit, SRAM, TS 35 ns (data retention) 03 see 6.6 64K x 1-bit, SRAM, TS 45 ns 04 see 6.6 64K x 1-bit, SRAM, TS 45 ns (data retention) 05 see 6.6 64K x 1-bit, SRAM, TS 55 ns 06 see 6.6 64K x 1-b

8、it, SRAM, TS 55 ns (data retention) 07 see 6.6 64K x 1-bit, SRAM, TS 70 ns 08 see 6.6 64K x 1-bit, SRAM, TS 70 ns (data retention) 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See Figure 1

9、 22 dual-in-line package Y See Figure 2 22 dual-in-line package Z See Figure 3 22 chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. Input voltage range . -0.5 V dc to VCC+ 0.5 V dc Storage temperature range . -65C to +

10、150C Lead temperature (soldering, 10 seconds) . +270C Thermal resistance, junction-to-case (JC) Case X . +15C / W 1/ Case Y . +30C / W 1/ Case Z . +30C / W 1/ Output voltage applied -0.5 V dc to +7.0 V dc Output current . 50 mA Maximum power dissipation (PD) 1.0 W Maximum junction temperature (TJ) .

11、 +150C 1.4 Recommended operating conditions. Supply voltage range 4.5 V dc minimum to 5.5 V dc maximum Input high voltage . 2.2 V dc to VCC+0.5 V Input low voltage -0.5 V dc to +0.8 V dc Fanout current with output high (each) . 4.0 mA Case operating temperature range (TC) . -55C to +125C 1/ When a t

12、hermal resistance value is listed in MIL-STD-1835, it shall supersede the value stated herein.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86015 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEV

13、EL C SHEET 3 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cit

14、ed in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outline

15、s. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Bui

16、lding 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exe

17、mption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML)

18、certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as docum

19、ented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535

20、 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on

21、 figure 4. 3.2.2 Truth table. The truth table shall be as specified on figure 5. 3.2.3 Functional block diagram. The functional block diagram shall be as specified on figure 6. 3.2.4 Case outlines. The case outlines shall be in accordance with figure 1 and 1.2.2 herein. 3.2.5 Die overcoat. Polyimide

22、 and silicone coatings are allowable as an overcoat on the die for alpha particle protection only. Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883).

23、The frequency of the internal water vapor testing shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain the requirements as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal. Provided by IHSNot for ResaleNo reprodu

24、ction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86015 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical perf

25、ormance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Ma

26、rking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in com

27、pliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer

28、in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix

29、A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be re

30、quired for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime s agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available

31、onshore at the option of the reviewer. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior t

32、o quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing

33、or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified i

34、n table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The

35、 following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CIN,COUTmeasurements) shall be measured only for the initial test and after process or

36、 design changes which may affect input or output capacitance. d. Subgroups 7 and 8 test sufficient to verify truth table of figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86015 DLA LAND AND MARITIM

37、E COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ 2/ 3/ Group A subgroups Device type Limits Unit Min Max High level output voltage VOHIOH= -4.0 mA, VIH= 2.2 V, VIL= 0.8 V 1, 2, 3 All 2.4 V Low level

38、output voltage VOLIOL= +8.0 mA, VIL= 0.8 V, VIH= 2.2 V 1, 2, 3 All 0.4 V High impedance (off-state) output leakage current IOLZCS VIH, VOH= 0.0 V VCC = 5.5 V 1, 2, 3 All -10 10 A IOHZCS VIH, VOH= 5.5 V VCC = 5.5 V 1, 2, 3 All -10 10 A High level input leakage current IIHVIH= 5.5 V, VCC= 5.5 V 1, 2,

39、3 All -10 10 A Low-level input leakage current IILVIL= 0.0 V, VCC= 5.5 V 1, 2, 3 All -10 10 A Operating supply current ICC1DOUT= open, CS = VILVCC = 5.5 V 1, 2, 3 03,05,07 105 mA 01,02,04, 06,08 90 DC supply current ICC2DOUT = open, CS = VILMinimum read cycle time VCC= 5.5 V 1, 2, 3 03,05,07 120 mA

40、02 70 01,04,06,08 95 Standby supply current (TTL) ICC3CS VIH, VCC= 5.5 V, Inputs = 0.8 V or 2.2 V 1, 2, 3 03.05,07 50 mA 01,02,04,06,08 35 Full standby supply current (CMOS) ICC4CS VCC- 0.2 V, VCC= 5.5 V Inputs: VCC- 0.2 V or 0.2 V 1, 2, 3 All 20 mA Data retention current 4/ ICCDRVDR= 2.0 V, CS VCC-

41、 0.2 V Inputs: VCC- 0.2 V or 0.2 V 1, 2, 3 02,04,06,08 1 mA Input capacitance CINVIN= 0.0 V, 5/ VCC= 5.0 V, f = 1 MHz VOUT= 0.0 V (see 4.3.1c) 4 All 8 pF Output capacitance COUTAll 10 pF Data retention voltage 4/ VDRCS = VDR, Inputs: VDR- 0.2 V or 0.2 V 1, 2, 3 02,04,06,08 2.0 5.5 V Functional tests

42、 See 4.3.1d VIL= 0.0 V, VIH= 3.0 V 7, 8 All See footnotes at end of table Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-86015 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FO

43、RM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ 2/ 3/ Group A subgroups Device type Limits Unit Min Max Address access time tAVQV9, 10, 11 07,08 70 ns 05,06 55 03,04 45 01,02 35 Output hold time tAXQX9, 10, 11 All 3 ns Read cycle time tELEH9, 10,

44、 11 07,08 70 ns 05,06 55 03,04 45 01,02 35 Chip enable access time tELQV9, 10, 11 07,08 70 ns 05,06 55 03,04 45 01,02 35 Chip enable to output active tELQX6/ 9, 10, 11 All 5 ns Chip disable to output disable 7/ tEHQZ6/ 9, 10, 11 All 0 40 ns Write cycle time tAVAV9, 10, 11 07,08 70 ns 05,06 55 03,04

45、45 01,02 35 Chip enable to end of write tELWH9, 10, 11 05,06,07,08 55 ns 03,04 40 01,02 30 Address valid to write high tAVWH9, 10, 11 05,06,07,08 55 ns 03,04 40 01,02 30 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-S

46、TANDARD MICROCIRCUIT DRAWING SIZE A 5962-86015 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ 2/ 3/ Group A subgroups Device type Limits Unit Min Max Write high to a

47、ddress dont care tWHAX9, 10, 11 All 5 ns Write pulse width tWLEH9, 10, 11 01,02 25 ns 03-08 40 Address setup to beginning of write tAVWL9, 10, 11 01,02 5 ns 03-08 15 Data valid to write high tDVWH9, 10, 11 01,02 20 ns 03,04,05,06 25 07,08 30 Write high to data dont care tWHDX9, 10, 11 All 5 ns Write

48、 enable to output disable 7/ tWLQZ6/ 9, 10, 11 01,02 0 20 ns 03-06 0 30 07,08 0 35 Output active after end of write tWHQX6/ 9, 10, 11 All 0 ns Address setup before chip enable tAVEL9, 10, 11 All 5 ns Chip enable high to address dont care tEHAX9, 10, 11 All 5 ns Data valid to chip enable high tDVEH9,

49、 10, 11 01,02 20 ns 03,04, 05,06 25 07,08 30 Chip disable to data retention time 8/ tCDR4/ 9, 10, 11 02,04 45 ns 06,08 70 Data retention recovery time 8/ tR4/ 9, 10, 11 02,04 45 ns 06,08 70 Chip select to power-up time 8/ tPU9, 10, 11 All 0 ns Chip deselect to power-down time 8/ tPD9, 10, 11 01-04 0