DLA SMD-5962-83013 REV D-1995 MICROCIRCUIT DIGITAL CMOS 8-BIT MICROPROCESSOR CPU MONOLITHIC SILICON《硅单片中央处理机的8比特微处理器 氧化物半导体数字微型电路》.pdf

《DLA SMD-5962-83013 REV D-1995 MICROCIRCUIT DIGITAL CMOS 8-BIT MICROPROCESSOR CPU MONOLITHIC SILICON《硅单片中央处理机的8比特微处理器 氧化物半导体数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-83013 REV D-1995 MICROCIRCUIT DIGITAL CMOS 8-BIT MICROPROCESSOR CPU MONOLITHIC SILICON《硅单片中央处理机的8比特微处理器 氧化物半导体数字微型电路》.pdf（21页珍藏版）》请在麦多课文档分享上搜索。

1、 DEFENSE LOGISTICS AGENC m 9999996 0068353 577 m DEFENSE ELECTRONICS SUPPLY CENTER 1507 WILMINGTON PIKE DAYTON, OH 45444- 5765 DESC-ELDC (Mr. L. Gauder/(AV 986) 513-296-852611tg) 0 4 MAY 1995 SUBJECT: Notice of Revision (NOR) 5962-R115-95 for Standard Microcircuit Drawing (SMD) 83013. Military/Indus

2、try Distribution The enclosed NOR is approved for use effective as of the date of the NOR. In accordance with MIL-STD-100 SMD holders should, as a minimum, handwrite those changes described in the NOR to sheet 1 of the subject SMD. After completion, the NOR should be attached to the subject SMD for

3、future reference. Those companies who were listed as approved sources of supply prior to this action have agreed to actions taken on devices for which they had previously provided DESC a certificate of compliance. This is evidenced by an existing active current certificate of compliance on file at D

4、ESC along with a DESC record of verbal coordination. The certificate of compliance for these devices is considered concurrence with the new revision unless DESC is otherwise notified. If you have comments or questions, please contact Larry T. Cauder at (AV)986-8526/(513)296-8526. 2 Encl IMONICA L. P

5、OELKING Chief, Custom Microelectronics Branch Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-rn 99999 NOTICE OF REVISION (NOR) a. (X one) X This revision described belou has been authorized for the document listed. (1) Existing document supplemented

6、 by the NOR may be used in manufacture. (2) Revised document must be received before manufacturer may incorporate this change. (3) Custodian of master document shall make above revision and furnish revised document. lb OOb352 403 rn d. TITLE Chief, Custom Microelectronics Form Approved I. YIIIC (YYM

7、MDD) I OM0 NO. 0704-0188 e. SIGNATURE Monica L. Poelking 95-04-13 I 15a. ACTIVITY ACCOMPLISHING REVISION DESC-ELDC lublic reporting-burden for this collection is estimated to average 2 hours per response ,he time for reviewin iata needed, and compfeting and reviewing the collection of information. S

8、end comments regarding this burden estimate or an other aspect of this collection of information, including suggestions For reducin this burden o De rtment of Defense Washingtion Headquarters Services Di rectorate For Informafion Operatiov and E Orts 1215 Jeffeison Davis Highway, Su!te 1204, ArlSn t

9、on VA ?2202-4302, and to the Office of Rana add ID“. Revisions description column; add “Changes in accordance with NOR 5962-R115-95“ Revisions date column; add “95-04-13 I. Revision level block; add “D“. Rev status of sheets; For sheets 1, 5, and 7 change to “D“. Table I: Address setup time tSAD, de

10、vice type 01: delete “45 ns minimum and substitute “105 ns mi ni mum“. Revision level block; change to “D“. Table I: XIN to clock falling tXcF, device type 01: delete “15 ns minimum and substitute “5 ns minimum“. Table I: XIN to clock rising txcR, device type 01; delete “15 ns minimum“ and substitut

11、e “5 ns minimum“. Revision level block; change to DI. Sheet 5: Sheet 7: Monica L. Poelking f. DATE SIGNED (YYMMDD) 95-04-1 3 c. DATE SIGNED (YYMMDD) 95-04-1 3 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-b 0068353 J-YS- 17 Change electrical perfor

12、mance characteristics. Add foatnote to figure 3. Change drawing CAGE code to 67268. Change fmax for device type 02 to 3.5 MHz. Editorial changes throughout, CURRENT CAGE CODE 67268 T989 Sept 6 I7)3013 REVISION LEVEL 1 AM$C NIA C SHEET 1 OF 19 I ESC FORM 193-1 auS.MRMMlmimnoWX: 1947-74S119/60912 SEP

13、87 5962-El 264 DISTRIBUTION STATEMENT A. Approved for ppbllo relesse; disirlbullon le unllmlted. 34T W Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-.P SIZE A STANDARDtZED . W 9999996 0068354 286 83013 1. SCOPE 1.1 SCO e. This drawingIldescribes de

14、vice requirements for class B microcircuits in accordance ith 1.hall affirm that the manufacturers product meets the requirements of MIL-STO-883 (see 3.1 herein) ind the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-STD-883 (see 3.1 herein) shal

15、l be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DESC-ECS shall be required in accordance iith MIL-STD-883 ( see 3.1 herei ni. 3.9 Verification and review. DESC, DESCs agent, and the acquiring activity retain the option to

16、.eview the manufacturers facfli ty and applicable required documentation. Offshore documentation ;hall be made available onshore at the option of the reviewer. 4. QUALITY ASSURANCE PROVISIONS 4.1 Samplin and inspection. Sampling and inspection procedures shall be in accordance with iection 4 of MPL-

17、M-tJi t o the extent specified in MIL-STD-883 (see 3.1 herein). 4.2 Screenin . Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be :onducte 4 on a devices prior to quality conformance inspection. The following additional criteria ;hall apply: a. Burn-in test, method 1015 o

18、f MIL-STD-883. (1) Test condition 0, using the circuit submitted with the certificate of compliance (see 3.6 herein). (2) TA = 125*C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are opti

19、onal at the discretion of the manufacturer. 4.3 Qualit conformance ins ection. Quality conformance inspection shall be in accordance with iethod 5005 o: MIL-STD-883 incyuding groups A, B, C, and D inspections. The following additional :riteria shall apply. 4.3.1 Group A inspection. a. Tests shall be

20、 as specified in table II herein. b. Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CIN and COUT measurements) shall be measured only for the initial test and after process or design changes which may affect capacitance. A minimum sample size of 5 devices

21、 with zero rejects shall be required. d. Subgroups 7 and 8 functional testing shall include verification of instruction set. 1 I 4 U. S. GOVERNMENT PRINTIN0 OFFNE l-B-W4 ESC FORM 193A SEP a7 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-= b 00b83b8

22、 870 - STANDARDIZU) SIZE A MILTTARY DRAWING 4.3.2 Groups C and 0 inspections. a, End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of ML-SEI-883: 11) (2) TA = 125?, minimum. (3) Test duration: 1,000 hours, except as permitted

23、by method 1005 of MIL-STD-883. Test condition D, using the circuit submitted with the certificate of compl3ance (see 3.6 herein). TABLE II. Electrfcal test requirements. I I Subgroups 1 1 Mit-STD-883 test requirements I (per methud I I 1 5005, table I) I I I I I I l I Interim electrical parameters I

24、 1 1 I (method 5004) I I I I 1 T - 83013 I Final electrical test parameters 1 1*, 2, 3, ?, 8, I I (method 50041 I 9, 10, 11 I I 1 1 I Group R test requirements I 1, 2, 3, 4, 7, I I (method50051 1 8, 9, 10, 11 1 I I 1 I Group C end-point electrical I 1, 2, 3 I I parameters (method 5005) I 1 I I I I G

25、roup 0 end-point electrical 1 1 I I parameters (method 5005) I I 1 1 I I I Additional electrical subgroups I I for group C periodic inspections 1 I * PDA applies to subgroup 1. - 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with 6. NOTES 6.1 Intended

26、 use. Microcircuits conforming to this drawjng are intended for use when military iecficatlons do not exist and quaJifi4 military devices that will perform the required function -e not available for OEM spplicatlon. When a military specification exists and the product covered / this drawing has been

27、 qualified for listing on QPL-38510, the device specified herein will be iactivated and will not be used for new design. The QPL-38510 product shall be the preferred item )r al 1 applications. 6.2 Re laceabilit . Microcircuits covered by this drawing will replace the same generic device L-M-SlO. wer

28、e + y a contractor-prepared specification or drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-9 9b 00b83b 707 SIZE 83013 STANDARDIZED A MILITARY DRAWING I DEFENSE ELECTRONICS SUPPLY CENTER REVEON LEVU SHEET DAYTON, OHIO 45444 C 17 + 6.3 Confi

29、guration control of SMDs. All proposed changes to existing SMDs will be coordinated with the users of record for the individual documents. This coordination will be accomplished in accordance with MIL-STO-481 using DO Form 1693, Engineering Change Proposal (Short Form). Center when a system applicat

30、ion requires configuration control and the applicable SMD. DESC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should contact DESC-ECS, telephone (513) 296-6022. 6

31、.4 Record of users. Military and industrial users shall inform Defense Electronics Supply 6.5 Comments. Comments on this drawing should be directed to DESC-ECS, Dayton, Ohio 45444, or telephnm 296-5375. I 6.6 Symbols, definitions, and functional descriptions. The symbols, definitions, and functional

32、 descriptions for this device shall be as follows: I SYSTEM DEFINITIONS I I Symbol Function wv m Reset input: Active low. Sets A(8-15) and AD(0-7) to three-state (high impedance). Clears the contents of PC, I and R registers, disables interrupts, and causes a reset output to be activated. Bus reques

33、t: Active low. Used when another device is requesting the system bus. RD and E are set to the high im edance mode and the re- quest is acknowledged via the cycle, the A8-151 bus is in the three-state mode. Reset out: Active high. When RESET OUT is high, it indicates the CPU is being reset. The signa

34、l is normally used to reset the peri- pheral devices. Input/output/memory: An active high on the IOP output signifies that the current machine cycle is relative to an inputioutput device. An active low on the lO/M output signifies that the current machine cycle is relative to memory. It is three-sta

35、te during mm cycles. Refresh: Active low. The refresh out ut indicates that the dynamic RAM refresh cycle is in progress. RFsf; goes low during T3 and T4 states of all M1 cycles. Address latch enable: ALE is active only during the T1 state of M cycles and T3 state of M1 cycles. The high to low trans

36、ition of ALE indicates that a valid memory/XO/refresh address is available on the AD(0-7) lines. Read strobe: Active low. On the trailing edge of the Rb strobe, data are input to the CPU via the AD(0-7) lines. The Kb line is in the three-state mode during mm cycles. Write strobe: While the CPU on th

37、e AD(0-7) lines. The iJR line is in the three-state mode during IfRWEK cyies. Clock: CLK is an output provided for use as a system clock. The CLK output is a square wave at one half the input frequency. - These are the most significant 8 line is low, valid data are output by the I I DEFENSE ELECTRON

38、ICS SUPPLY CENTER MYTON. OHIO 45.444 I SHEET 18 b I I I t U. S GOVERNMENT PRINTING OFFICE 1088-549-8M DESC FORM 193A SEP a7 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Symbol Function SIZE A STANDARDIZED m 83013 I so*s1 Interrupt acknowledge: Act

39、ive 1 ow. The interrupt acknowledge output is activated in the M1 cycle (SI immediately following the state in which the 1NTR input is recognized. (Output is normally used to gate the interrupt response vector from the peripheral controller onto the AD(0-7) lines.) It is used in two of the three int

40、errupt modes. In mode O, an instruction is gated onto the AD(0-7) line during TATA. In mode 2, a single interrupt response vector is gated onto the data bus. Status. Bus status outputs indicate encoded information regarding the ensuing M cycle as follows: STATE - - s1 gj O0 HALT o1 WRITE 10 READ 11

41、( OPCODE) FETCH 6.7 Approved source of supply. An approved source of supply is listed in MIL-BUL-103. Additional sources will be added to MIL-BUL-103 as they become available. The vendor listed in MIL-BUL-103 has agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submit

42、ted to and accepted by DESC-ECS. The approved source of supply listed below is for information purposes only and is current only to the date of the last action of this document. I I Vendor I V endor I I Military drawing I CAGE I similar part I I part number I number I number L/ I I I I I I I I 27014

43、 I NSC800D/883B I I I 8301301QX I 8301301ZX I 27014 I NSC800E/883B I I 8301302QX I 27014 I NSC800D-35/883 I I 8301302ZX I 27014 I N!X800E-35/883 I I I I I i/ Caution. Do not use this number for item - wtion. Items acquired to this number may not satisfy the performance requirements of this drawing.

44、Vendor CAGE number 27014 Vendor name and address National Semiconductor Corporation 2900 Semiconductor Drive Santa Clara, CA 95051 EFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL CHER I DAYTON, OHIO 45444 C 19 DESC FORM 193A t U 8 QOVERNMENT PRINTINQ OFFICE 1988-550-541 1 I 4 SEP 87 . . r Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-