DLA SMD-5962-05206 REV B-2009 MICROCIRCUIT DIGITAL-LINEAR CMOS LOW POWER DUAL 8-BIT 1 GSPS ANALOG-TO-DIGITAL CONVERTER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add radiation hardened requirements. Add paragraphs 1.5, 3.2.3, 4.4.4.1, and 4.4.4.1.1. Add one footnote to Table I. Make changes to Table II. Add Table IB. - ro 07-07-03 R. HEBER B Add VIN+ and VIN- limits to paragraph 1.3. Make changes to VIN+

2、and VIN- limits as specified under paragraph 1.4. - ro 09-06-23 C. SAFFLE REV SHET REV B B B B B B B SHEET 15 16 17 18 19 20 21 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO

3、43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY RAJESH PITHADIA APPROVED BY JOSEPH RODENBECK MICROCIRCUIT, DIGITAL-LINEAR, CMOS, LOW POWER, DUAL 8-BIT, 1 GSPS ANALOG-TO-DIGITAL C

4、ONVERTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 07-01-29 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-05206 SHEET 1 OF 21 DSCC FORM 2233 APR 97 5962-E356-09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZ

5、E A 5962-05206 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choic

6、e of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 F 05206 01 V Z C Federal stock clas

7、s designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the ap

8、propriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device typ

9、e Generic number Circuit function 01 ADC08D1000 Low power, dual 8-bit, 1 GSPS analog-to-digital converter 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-cer

10、tification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline lett

11、er Descriptive designator Terminals Package style Z See figure 1 128 Quad leaded chip carrier with gull wing leads 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduct

12、ion or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-05206 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage ( VA, VDR) 2.2 V Voltage on any input pi

13、n -0.15 V to ( VA+0.15 V ) Ground difference |GND DR GND| . 0 V to 100 mV Voltage on VIN+, VIN-(maintaining common mode) . -0.15 V to 2.5 V Input current at any pin . 25 mA 3/ Package input current . 50 mA 3/ Power dissipation (PD) at TA +85C . 2.0 W Electrostatic discharge susceptibility: 4/ Human

14、body model 6000 V Soldering temperature, infrared (10 seconds) . +235C Storage temperature . -65C to +175C Thermal resistance, junction-to-ambient (JA) 11.5C/W Thermal resistance, junction-to-case (JC) . 3.8C/W Thermal pad resistance (J-PAD) 2.0C/W 1.4 Recommended operating conditions. 1/ 2/ Supply

15、voltage (VA) . +1.8 V to +2.0 V Driver supply voltage (VDR) +1.8 V to VAAnalog input common mode voltage . VCMO50 mV VIN+, VIN- voltage range (maintaining common mode) : 100% duty cycle . 0 V to 2.15 V 10% duty cycle 0 V to 2.5 V Ground difference ( IGND DR GNDI ) 0 V CLK pins voltage range . 0 V to

16、 VADifferential CLK amplitude 0.4 VPPto 2.0 VPPMaximum junction temperature (TJ) +150C Ambient temperature range (TA) . -55C to +125C 1.5 Radiation features. Maximum total dose available . 300 krads (SiO2) Single event latch-up (SEL) 120 MeV-cm2/mg 5/ _ 1/ Stresses above the absolute maximum rating

17、may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ All voltages are measured with respect to GND = DR GND = 0 V, unless otherwise specified. 3/ When the input voltage at any pin exceeds the power supply limits ( that

18、is, less than GND or greater than VA), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. This limit is not placed upon the power, ground and dig

19、ital output pins. 4/ Human body model is 100 pF capacitor discharged through a 1.5 k resistor. 5/ Limits are based on characterization, but not production tested unless specified by the customer through the purchase order or contract. Provided by IHSNot for ResaleNo reproduction or networking permit

20、ted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-05206 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standa

21、rds, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

22、 DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of th

23、ese documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited h

24、erein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance wit

25、h MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38

26、535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for dev

27、ice class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer un

28、der document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation par

29、ameter limits are as specified in table IA and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table IA. 3.5 Marking.

30、The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA produ

31、ct using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device class

32、es Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962

33、-05206 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. Test Symbol Conditions 1/ 2/ 3/ 4/ -55C TA+125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxStatic converte

34、r characteristics Integral non-linearity (best fit) INL DC coupled, 1 MHz sine wave overanged 1,2,3 01 0.9 LSB Differential non-linearity DNL DC coupled, 1 MHz sine wave overanged 1,2,3 01 0.6 LSB Resolution with no missing codes 1,2,3 01 8 Bits Offset error VOFF1,2,3 01 -1.5 0.5 LSB Positive full s

35、cale error PFSE 5/ 1,2,3 01 27 mV Negative full scale error NFSE 5/ 1,2,3 01 27 mV Out of range output code (In addition to OR output high) (VIN+) (VIN-) + full scale 1,2,3 01 255 (VIN+) (VIN-) - full scale 0 Analog input and reference characteristics Full scale analog differential input range VINFS

36、R pin high 1,2,3 01 790 950 mVP-PDifferential input resistance RIN1,2,3 01 94 106 Analog output characteristics Common mode output voltage VCMO1,2,3 01 0.95 1.45 V Bandgap reference output voltage VBGIBG= 100 A 1,2,3 01 1.20 1.33 V Clock input characteristics Differential clock input level VIDSine w

37、ave clock 1,2,3 01 0.5 2.0 VP-PSquare wave clock 0.5 2.0 Digital control pin characteristics Logic high input voltage VIH1,2,3 01 0.85 x VAV Logic low input voltage VIL1,2,3 01 0.15 x VAV See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without lice

38、nse from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-05206 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics Continued. Test Symbol Conditions 1/ 2/ 3/ 4/ -55C TA+125C unless otherwise specif

39、ied Group A subgroups Device type Limits Unit Min MaxDigital output characteristics LVDS differential output voltage VODMeasured differentially, 6/ OutV = VA, VBG = floating 1,2,3 01 400 920 mVP-P Measured differentially, 6/ OutV = GND, VBG = floating 280 720 Power supply characteristics Analog supp

40、ly current IAPD = PDQ = low 1,2,3 01 765 mA PD = low, PDQ = high 508 Output driver supply current IDRPD = PDQ = low 1,2,3 01 275 mA PD = low, PDQ = high 157 Power consumption PDPD = PDQ = low 1,2,3 01 1.97 W PD = low, PDQ = high 1.27 Normal mode (non DES) dynamic converter characteristics Effective

41、number of bits ENOB fIN= 248 MHz, VIN= FSR 0.5 dB 4,5,6 01 7.0 Bits fIN= 498 MHz, VIN= FSR 0.5 dB 7.0 Signal to noise plus distortion ratio SINAD fIN= 248 MHz, VIN= FSR 0.5 dB 4,5,6 01 43.9 dB fIN= 498 MHz, VIN= FSR 0.5 dB 43.9 Signal to noise ratio SNR fIN= 248 MHz, VIN= FSR 0.5 dB 4,5,6 01 44 dB f

42、IN= 498 MHz, VIN= FSR 0.5 dB 44 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-05206 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM

43、 2234 APR 97 TABLE IA. Electrical performance characteristics Continued. Test Symbol Conditions 1/ 2/ 3/ 4/ -55C TA+125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxNormal mode (non DES) dynamic converter characteristics - continued Total harmonic distortion THD fIN=

44、248 MHz, VIN= FSR 0.5 dB 4,5,6 01 -47.5 dB fIN= 498 MHz, VIN= FSR 0.5 dB -47.5 Spurious free dynamic range SFDR fIN= 498 MHz, VIN= FSR 0.5 dB 4,5,6 01 47 dB Maximum input clock frequency fCLK1Normal mode (non DES) 4,5,6 01 1.0 GHZ Interleave mode (DES pin = float) dynamic converter characteristics E

45、ffective number of bits ENOB fIN= 498 MHz, VIN= FSR 0.5 dB 4,5,6 01 6.8 Bits Signal to noise plus distortion ratio SINAD fIN= 498 MHz, VIN= FSR 0.5 dB 4,5,6 01 42.5 dB Signal to noise ratio SNR fIN= 498 MHz, VIN= FSR 0.5 dB 4,5,6 01 43 dB Total harmonic distortion THD fIN= 498 MHz, VIN= FSR 0.5 dB 4

46、,5,6 01 -49 dB Spurious free dynamic range SFDR fIN= 498 MHz, VIN= FSR 0.5 dB 4,5,6 01 47 dB AC timing parameters Reset pulse width tRPW9,10,11 01 4 Clock cycles Serial clock low time 9,10,11 01 4 ns Serial clock high time 9,10,11 01 4 ns See footnotes at end of table. Provided by IHSNot for ResaleN

47、o reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-05206 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 8 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics Continued. Test Symbol Conditio

48、ns 1/ 2/ 3/ 4/ -55C TA+125C unless otherwise specified Group A subgroups Device type Limits Unit Min MaxAC timing parameters - continued CAL pin low time tCAL_LSee figure 3 9,10,11 01 640 Clock cycles CAL pin high time tCAL_HSee figure 3 9,10,11 01 640 Clock cycles 1/ The following specifications apply after calibration for VA= VDR= +1.9 VDC, OutV = 1.9 V, VINFSR (a.c. coupled) = differential 870 mVP-P, CL= 10 pF, differential, a.c. coupled sinewave i