DLA DSCC-VID-V62 04730 REV A-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVER MONOLITHIC SILICON.pdf
《DLA DSCC-VID-V62 04730 REV A-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVER MONOLITHIC SILICON.pdf》由会员分享,可在线阅读,更多相关《DLA DSCC-VID-V62 04730 REV A-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVER MONOLITHIC SILICON.pdf(15页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Update boilerplate paragraphs to current requirements. - PHN 11-08-22 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing RE
2、V PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED
3、BIPOLAR CMOS, 3.3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVER, MONOLITHIC SILICON YY-MM-DD 04-06-09 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04730 REV A PAGE 1 OF 15 AMSC N/A 5962-V072-11 Provided by IHSNot for ResaleNo reproduction or networking permitted
4、 without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04730 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 3.3-V ABT scan test device with 18-bit universal bus transceiver microcirc
5、uit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04
6、730 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVTH182512-EP 3.3-V ABT scan test device with 18-bit universal bus transceiver 1.2.2 Case outlines. The case outlines are as specifie
7、d herein. Outline letter Number of pins JEDEC PUB 95 Package style X 64 JEDEC MO-153 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plate C Gold
8、plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04730 REV A PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage
9、 range (VCC) . -0.5 V to +4.6 V Input voltage range (VI) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high state or power-off state (VO) -0.5 V to 7 V 2/ Current into any output in the low state (IO): (A port or TDO) 128 mA (B port) 30 mA Current into any output in the high state (I
10、O): 3/ (A port or TDO) 64 mA (B port) 30 mA Input clamp current (IIK) (VIVCC. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. 5/ Unused control inputs must be held high or low to prevent them from floating. 6/ Current duty cycle 50%, f 1 kHz. Provided by IHSNot for Resal
11、eNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04730 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for S
12、emiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at http:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) THE
13、INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE) IEEE Standard 1149.1 - IEEE Standard Test Access Port and Boundary Scan Architecture. (Copies of these documents are available online at http:/www.ieee.org or from the IEEE Service Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 088551331
14、. 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marke
15、d with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dime
16、nsion. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Function table. The function table shall be as shown in figure 2. 3.5.3 Functional block diagram. The functional block d
17、iagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted
18、 without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04730 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Input clamp voltage VIKII= -18 mA 2.7 V
19、 25C, -40C to 85C All -1.2 V High level output voltage VOHA, B, TDO, IOH= -100 A 2.7 V to 3.6 V VCC 0.2 V A port, TDO, IOH= -3 mA 2.7 V 2.4 A port, TDO, IOH= -8 mA 3 V 2.4 A port, TDO, IOH= -32 mA 2 B port, IOH= -12 mA 2 Low level output voltage VOLA, B, TDO, IOL= 100 A 2.7 V 0.2 V A port, TDO, IOL=
20、 24 mA 0.5 A port, TDO, IOL= 16 mA 3 V 0.4 A port, TDO, IOL= 32 mA 0.5 A port, TDO, IOL= 64 mA 0.55 B port, IOL= 12 mA 0.8 Input current IICLK, LE, TCK VI= VCCor GND 3.6 V 1 A CLK, LE, TCK, VI= 5.5 V 0 V or 3.6 V 10 OE, TDI, TMS, VI= 5.5 V 3.6 V 5 OE, TDI, TMS, VI= VCC1 OE, TDI, TMS, VI= 0 V -25 -10
21、0 A or B ports, VI= 5.5 V 2/ 20 A or B ports, VI= VCC2/ 1 A or B ports, VI= 0 V 2/ -5 Input/output power-off leakage current IoffVIor VO= 0 V to 4.5 V 0 V 100 Input current (hold) II(hold)3/ A or B ports, VI= 0.8 V 3 V 75 500 A or B ports, VI= 2 V -75 -500 Off-state output current high IOZHTDO VO= 3
22、 V 3.6 V 1 Off-state output current low IOZLTDO VO= 0.5 V 3.6 V -1 3-state output current power-up IOZPUTDO VO= 0.5 V or 3 V 0 V to 1.5 V 50 3-state output current power-down IOZPDTDO VO= 0.5 V or 3 V 1.5 V to 0 V 50 Quiescent supply current ICCOutputs high. VI= VCCor GND, IO= 0 A 3.6 V 2 mA Outputs
23、 low. VI= VCCor GND, IO= 0 A 24 Outputs disabled. VI= VCCor GND, IO= 0 A 2 Quiescent supply current delta ICC4/ One input at VCC 0.6 V, Other inputs at VCCor GND 3 V to 3.6 V 0.5 Input capacitance CiVI= 3 V or 0 V 3.3 V 25C 4 TYP pF Input/output capacitance CioVO= 3 V or 0 V 10 TYP Output capacitanc
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