DLA DSCC-VID-V62 04711 REV B-2011 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 3 3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS MONOLITHIC SILICON.pdf

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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Add new device case outline Y. Update boilerplate to current revision. - CFS 04-11-22 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 11-06-14 David J. Corbett CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAN

2、D AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Original date o

3、f drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, ADVANCED BIPOLAR CMOS, 3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS, MONOLITHIC SILICON YY-MM-DD 04-04-23 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04711 REV B PAGE 1 OF 12 AMSC N/A

4、 5962-V047-11 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04711 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high per

5、formance 3.3-V ABT 16-bit edge-triggered D-type flip-flop with 3-state outputs microcircuit, with an operating temperature range of -40C to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an adminis

6、trative control number for identifying the item on the engineering documentation: V62/04711 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVTH16374-EP 3.3-V ABT 16-bit edge-triggered

7、D-type flip-flop with 3-state outputs 1.2.2 Case outline. The case outline are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 48 MO-153 Plastic small-outlineY 48 MO-118 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead

8、finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO

9、SIZE A CODE IDENT NO. 16236 DWG NO. V62/04711 REV B PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V to 4.6 V Input voltage range (VI) . -0.5 V to 7 V 2/ Voltage range applied to any output in the high-impedance or power-off state (VO) . -0.5 V to 7 V 2/ Voltage range appl

10、ied to any output in the high state (VO) . -0.5 V to VCC+ 0.5 V 2/ Current into any output in the low state (IO) . 128 mA Current into any output in the high state (IO) . 64 mA 3/ Input clamp current (IIK) (VI 0) -50 mA Output clamp current (IOK) (VO 0) . -50 mA Package thermal impedance (JA) . 70C/

11、W 4/ Storage temperature range (TSTG) . -65C to 150C 1.4 Recommended operating conditions. 5/ Supply voltage range (VCC) . 2.7 V to 3.6 V Minimum high level input voltage (VIH) 2.0 V Maximum low level input voltage (VIL) . 0.8 V Maximum input voltage (VI) . 5.5 V Maximum high level output current (I

12、OH) . -32 mA Maximum low level output current (IOL) . 64 mA Maximum input transition rise or fall rate (t/v) (Outputs enabled) 10 ns/V Minimum power-up ramp rate (t/VCC) 200 s/V Operating free-air temperature range (TA) -40C to +85C 1/ Stresses beyond those listed under “absolute maximum ratings” ma

13、y cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect

14、 device reliability. 2/ The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3/ This current flows only when the output is in the high state and VO VCC. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. 5

15、/ All unused control inputs of the device must be held at VCCor GND to ensure proper device operation. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04711 REV B

16、PAGE 4 2. APPLICABLE DOCUMENTS JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC PUB 95 Registered and Standard Outlines for Semiconductor Devices JEDEC STD 51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at h

17、ttp:/www.jedec.org or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, C

18、AGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electri

19、cal performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3

20、.5.2 Truth table. The truth table shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Terminal connections. The terminal connections shall be as shown in figure 4. 3.5.5 Test circuit and timing waveforms. The test circuit and timing waveforms sh

21、all be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04711 REV B PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Con

22、ditions VCCTemperature, TADevice type Limits Unit Min Max Input clamp voltage VIKII= -18 mA 2.7 V 25C, -40C to 85C All -1.2 V High level output voltage VOHIOH= -100 A 2.7 V to 3.6 V VCC 0.2 V IOH= -8 mA 2.7 V 2.4 IOH= -32 mA 3 V 2 Low level output voltage VOLIOL= 100 A 2.7 V 0.2 V IOL= 24 mA 0.5 IOL

23、= 16 mA 3 V 0.4 IOL= 32 mA 0.5 IOL= 64 mA 0.55 Input current IIVI= 5.5 V 0 V or 3.6 V 10 A Control inputs. VI= VCCor GND 3.6 V 1 Data inputs. VI= VCC1 Data inputs. VI= 0 V -5 Input/output power-off leakage current IoffVIor VO= 0 to 4.5 V 0 V 100 A Input current (hold) II(hold)Data inputs, VI= 0.8 V

24、3 V 75 AData inputs, VI= 2 V -75 Data inputs. VI= 0 V to 3.6 V 3.6 V 2/ 500 3-state output leakage current high IOZHVO= 3 V 3.6 V 5 A3-state output leakage current low IOZLVO= 0.5 V 3.6 V -5 A3-state output current power-up IOZPUVO= 0.5 V to 3 V OE = dont care 0 V to 1.5 V 100 A 3-state output curre

25、nt power-down IOZPDVO= 0.5 V to 3 V OE = dont care 1.5 V to 0 V 100 A Quiescent supply current ICCOutputs high. VI= VCCor GND, IO= 0 A 3.6 V 0.19 mA Outputs low. VI= VCCor GND, IO= 0 A 5 Outputs disabled. VI= VCCor GND, IO= 0 A 0.19 Quiescent supply current delta ICC3/ One input at VCC 0.6 V, Other

26、inputs at VCCor GND3 V to 3.6 V 0.2 mA Input capacitance CiVI= 3 V or 0 V 3.3 V 3 TYP pFOutput capacitance CoVO= 3 V or 0 V 9 TYP pFSee footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBU

27、S, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04711 REV B PAGE 6 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions VCCTemperature, TADevice type Limits Unit Min Max Clock frequency fclock2.7 V 25C, -40C to 85C All 160 MHz 3.3 V 0.3 V 160 Pulse duration, CLK high o

28、r low twSee figure 5. 2.7 V 3 ns 3.3 V 0.3 V 3 Setup time, data before CLK tsuHigh or low See figure 5. 2.7 V 2 ns 3.3 V 0.3 V 1.8 Hold time, data after CLK thHigh or low See figure 5. 2.7 V 0.1 ns 3.3 V 0.3 V 0.8 Maximum frequency fmaxCL= 50 pF 2.7 V 160 MHz 3.3 V 0.3 V 160 Propagation delay time,

29、CLK to Q tPLHCL= 50 pF See figure 5. 2.7 V 5.2 ns 3.3 V 0.3 V 1.9 4.5 tPHL2.7 V 4.23.3 V 0.3 V 2.1 4 Propagation delay time, output enable, OE to Q tPZH2.7 5.43.3 V 0.3 V 1.5 4.5 tPZL2.7 V 5 3.3 V 0.3 V 1.5 4.4 Propagation delay time, output disable, OE to Q tPHZ2.7 5.43.3 V 0.3 V 2.4 5 tPLZ2.7 V 4.

30、83.3 V 0.3 V 2 4.6 Output skew tsk(0)CL= 50 pF 3.3 V 0.3 V 0.5 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all p

31、arameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. 3/ Th

32、is is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCCor GND. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO.

33、V62/04711 REV B PAGE 7 Case X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.20 - 0.047 E1 6.00 6.20 0.236 0.244 A1 0.05 0.15 0.002 0.006 e 0.50 BSC 0.020 BSC b 0.17 0.27 0.007 0.011 L 0.50 0.75 0.020 0.030 D 12.40 12.60 0.488 0.496 L1 0.25 TYP 0

34、.010 TYP E 7.90 8.30 0.311 0.327 L2 0.15 NOM 0.006 NOM NOTES: 1. All linear dimensions are in millimeters (inches). 2. This case outline is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.15 millimeters (0.006 in). 4. Fall within JEDEC MO

35、-153. FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04711 REV B PAGE 8 Case Y Dimensions Symbol Inches Millimeters Symbol Millimeters Inc

36、hes Min Max Min Max Min Max Min Max A - .110 - 2.79 E1 .291 .299 7.39 7.59 A1 .008 - 0.20 - e .025 BSC 0.635 BSC b .008 .0135 0.203 0.343 L .020 .040 0.51 1.02 D .620 .630 15.75 16.00 L1 .010 TYP 0.25 TYP E .395 .420 10.03 10.67 L2 .005 .010 0.13 0.25 NOTES: 1. All linear dimensions are in inches (m

37、illimeters). 2. This case outline is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 inches (0.15 millimeters). 4. Falls within JEDEC MO-118. FIGURE 1. Case outlines - Continued. Provided by IHSNot for ResaleNo reproduction or network

38、ing permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04711 REV B PAGE 9 (each flip-flop) Inputs Output Q OE CLK D L L L H H or L X H L X X H L Q0Z H = High voltage level X = Immaterial L = Low voltage level Z = High impedan

39、ce state Q0= Level of Q before the indicated steady-state input conditions were established. = Low to high transition FIGURE 2. Truth table. FIGURE 3. Logic diagram. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLU

40、MBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04711 REV B PAGE 10 Device type 01 Case outline X and Y Terminal number Terminal symbol Terminal number Terminal symbol 1 1OE 25 2CLK 2 1Q1 26 2D8 3 1Q2 27 2D7 4 GND 28 GND 5 1Q3 29 2D6 6 1Q4 30 2D5 7 VCC31 VCC8 1Q5 32 2D4 9 1Q6 33 2D3 10 GND 34 GND

41、 11 1Q7 35 2D2 12 1Q8 36 2D1 13 2Q1 37 1D8 14 2Q2 38 1D7 15 GND 39 GND 16 2Q3 40 1D6 17 2Q4 41 1D5 18 VCC42 VCC19 2Q5 43 1D4 20 2Q6 44 1D3 21 GND 45 GND 22 2Q7 46 1D2 23 2Q8 47 1D1 24 2OE 48 1CLK FIGURE 4. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted wit

42、hout license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04711 REV B PAGE 11 NOTES: 1. CLincludes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output

43、control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 , tr 2.5 ns, and tf 2.5 ns. 4. The outputs are measured one a

44、t a time with one input transition per measurement. FIGURE 5. Test circuit and timing waveforms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04711 REV B PAGE 1

45、2 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and la

46、beling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturers standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are ele

47、ctrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturers data book. The device manufacturer reserves the right to make changes without notice. This drawing will

48、be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. Vendor item drawing administrative control number 1/ Devic