DLA DSCC-VID-V62 04645 REV B-2012 MICROCIRCUIT DIGITAL-LINEAR DUAL OUTPUT TWO PHASE SYNCHRONOUS DC DC CONTROLLER MONOLITHIC SILICON.pdf

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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Add device 02. Update boilerplate. - PHN 06-04-26 Thomas M. Hess B Update boilerplate paragraphs to current requirements. - PHN 12-03-22 Thomas M. Hess CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-39

2、90 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV B B B B B B B B B B B B B B PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Original date of drawing YY MM DD CHECKED BY TOM

3、 HESS TITLE MICROCIRCUIT, DIGITAL-LINEAR, DUAL OUTPUT, TWO PHASE SYNCHRONOUS DC/DC CONTROLLER, MONOLITHIC SILICON 04-03-22 APPROVED BY RAYMOND MONNIN SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04645 REV B PAGE 1 OF 14 AMSC N/A 5962-V046-12 .Provided by IHSNot for ResaleNo reproduction or networking pe

4、rmitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04645 REV B PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance dual output, two phase synchronous DC/DC controller microcircuit, w

5、ith an operating temperature range of -40C to +125C (device 01) and extended temperature range of -55C to +125C (device 02). 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control numbe

6、r for identifying the item on the engineering documentation: V62/04645 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 TPS5120-EP Dual output, two phase synchronous DC/DC controller 02 TPS5

7、120-EP Dual output, two phase synchronous DC/DC controller 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 30 MO-153 Plastic small outline1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes

8、as provided by the device manufacture: Finish designator Material A Hot solder dip B Tin-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SI

9、ZE A CODE IDENT NO. 16236 DWG NO. V62/04645 REV B PAGE 3 1.3 Absolute maximum ratings. 1/ Supply voltage (VCC) -0.3 V to +30 V 2/ Input voltage: INV1, INV2, CT, PWM/SKIP, REG5V_IN, SOFTSTART1, SOFTSTART2, FLT, POWERGOOD pins . -0.3 V to +7 V STBY1, STBY2, 5V_STBY,TRIP1, TRIP2 pins -0.3 V to 30 V Out

10、put voltage: LL1, LL2 pins -1.0 V to 30 V OUT1_u, OUT2_u pins . -1.0 V to 35 V LH1, LH2 pins . -0.3 V to 35 V OUT1_d, OUT2_d, 5V_OUT, FB1, FB2 pins -0.3 V to 7 V REF pin -0.3 V to 3 V OUT1_u, LH1 to LL1 pins . -0.3 V to 7 V OUT2_u, LH2 to LL2 pins . -0.3 V to 7 V Power dissipation (TA 25C) ( PD) . 8

11、74 mW 3/ Operating junction temperature range (TJ) -55C to +150C Storage temperature range (TSTG) . -55C to +150C 1.4 Recommended operating conditions. 4/ Supply voltage range (VCC) 4.5 V minimum to 28 V maximum Input voltage range ( VI): INV1, INV2, CT, PWM/SKIP, SOFTSTART1, SOFTSTART2, FLT pins .

12、6 V maximum REG5V_IN, POWERGOOD pins -0.1 V minimum to 5.5 V maximum STBY1, STBY2, 5V_STBY pins 28 V maximum OUT1_u, OUT2_u, LH1, LH2 pins 33 V maximum TRIP1, TRIP2 pins -0.1 V minimum to 28 V maximum Oscillator frequency (fOSC) 500 kHz maximum Operating free air temperature range ( TA): Device 01 .

13、 -40C to +125C Device 02 . -55C to +125C Dissipation rating table. Case outline TA 25C power rating Derating factor above TA= 25C Power dissipation TA= 125C X 874 mW 6.993 mW/C 175 mW 1/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are

14、stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ All voltage values are wit

15、h respect to the network ground terminal unless otherwise noted. 3/ See dissipation rating table. 4/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for product used

16、beyond the stated limits.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04645 REV B PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standard Outlines f

17、or Semiconductor Devices (Applications for copies should be addressed to the Electronic Industry Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or at http:/www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown

18、 in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The m

19、aximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The

20、case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Logic chart. The logic chart shall be as shown in figure 4. 3.5.5 Timing waveforms. Th

21、e timing waveforms shall be as shown in figure 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04645 REV B PAGE 5 TABLE I. Electrical performance characteristic

22、s. 1/ Test Symbol Conditions VCC= 7 V 2/ unless otherwise specifiedTemperature, TALimits Unit Min Max Reference voltage section Reference voltage Vref 0.85 typical V Reference voltage tolerance Vref(tol) I = 50 A TA= +25C -1.5 1.5 % TJ= -55C to +125C -3.0 3.0 Line regulation R(egin) VCC= 4.5 V to 28

23、 V, I = 50 A 3 mV Load regulation R(egl) I = 0.1 A to 1 mA 5 mV Oscillator section Frequency fOSCPWM mode, CT = 44 pF TA=25C 300 typical kHz High level output voltage VOHDC 1.1 typical V fOSC= 300 kHz 1.17 typical Low level output voltage VOLDC 0.5 typical V fOSC= 300 kHz 0.43 typical Error amplifie

24、r section Input offset voltage VIOTA=25C 10 mV Open loop voltage gain 50 dB Unity gain bandwidth 2.5 typical MHz Output sink current I(snk) VO= 1 V 0.3 mA Output source current I(src) VO= 1 V 0.2 mA Skip comparator section Hysteresis window Vhys SKIP mode 9 typical mV Duty control section Maximum du

25、ty cycle DUTY 300 kHz, VI = 0 V 83 typical % See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04645 REV B PAGE 6 TABLE I. Electrical

26、performance characteristics continued. 1/ Test Symbol Conditions VCC= 7 V 2/ unless otherwise specifiedTemperature, TALimits Unit Min Max Control section High level input voltage VIHSTBY1, STBY2 2.2 V PWM/SKIP, 5V_STBY 2.2 Low level input voltage VILSTBY1, STBY2 0.3 V PWM/SKIP, 5V_STBY 0.3 5 V inter

27、nal switch section Threshold V(TO_H)4.2 4.8 V V(TO_L)4.1 4.7Hysteresis Vhys 30 200 mV 5 V regulator section Output voltage VOVCC= 5.5 V to 28 V, IO= 0 mA to 50 mA TA=25C 4.8 5.2 V Line regulation R(egin) VCC= 5.5 V to 28 V, I = 10 mA 20 mV Load regulation R(egl) VCC= 5.5 V, I = 1 mA to 10 mA 40 mV S

28、hort circuit output current IOS5VREG = 0 V TA=25C 65 mA UVLO threshold voltage V(TO_H)5V_OUT voltage 3.6 4.2 V V(TO_L)3.5 4.1Hysteresis Vhys 5V_OUT voltage 20 150 mV Output drivers section OUT_u sink current VO= 3 V 1.2 typical A OUT_u source current VO= 2 V -1.5 typical A See footnotes at end of ta

29、ble. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04645 REV B PAGE 7 TABLE I. Electrical performance characteristics continued. 1/ Test Symbol Conditions VCC= 7

30、 V 2/ unless otherwise specifiedTemperature, TALimits Unit Min Max Output drivers section - continued OUT_d sink current VO= 3 V 1.5 typical A OUT_d source current VO= 2 V -1.5 typical A TRIP pin current I(TRIP)TA=25C 11.5 14.5 A Soft start section Soft start current I(SOFT)1.6 2.9 A Threshold volta

31、ge V(TO_H)3.7 typical V (SKIP mode) V(TO_L)2.5 typicalOutput voltage monitor section OVP comparator threshold 0.91 0.99 V UVP comparator threshold 0.64 0.72 V PG comparator 1, 2 threshold 0.75 0.81 V PG comparator 3, 4 threshold 0.88 0.94 V PG propagation delay Turnon 13 typical s from INV to POWERG

32、OOD Turnoff 1.2 typical Timer latch current source UVP protection 1.5 3.1 A OVP protection 8 15 Supply current section Supply current ICCCT = 0 V, INV = 0 V TA=25C 1.5 mA Shutdown current ICC(S)STBY1, STBY2, 5V_STBY = 0 V TA=25C 10 A STBY1, STBY2, 5V_STBY = 0 V TA= -55C to 125C 20 1/ Testing and oth

33、er quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric te

34、sting, product performance is assured by characterization and/or design. 2/ For device 01 TA= -40C to +125C; for device 02 TA= -55C to +125C unless otherwise specified. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS C

35、OLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04645 REV B PAGE 8 Case X Dimensions Symbol Millimeters Inches Symbol Millimeters Inches Min Max Min Max Min Max Min Max A - 1.20 - 0.047 E 4.30 4.50 0.169 0.177 A1 0.05 0.15 0.002 0.006 E1 6.20 6.60 0.244 0.259 b 0.17 0.27 0.007 0.011 e 0.50 NOM

36、 0.019 NOM c 0.15 NOM 0.006 NOM L 0.50 0.75 0.019 0.029 D 7.70 7.90 0.303 0.311 NOTES: 1. This drawing is subject to change without notice. 2. Body dimensions do not include mold flash or protrusion. 3. Falls within JEDEC MS-153. FIGURE 1. Case outlines - Continued. Provided by IHSNot for ResaleNo r

37、eproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04645 REV B PAGE 9 Device type 01 Case outline X Terminal number Terminal symbol I/O Description 1 INV1 I Inverting input of the CH1 error amplifier

38、, skip comparator, and OVP1/UVP1 comparator. 2 FB1 O Feedback output of CH1 error amplifier 3 SOFTSTART1 I/O External capacitor from SOFTSTART1 to GND for CH1 softstart control. Separate soft-start terminals make it possible to set the start-up time of each output independently. 4 PWM/SKIP I PWM/SKI

39、P mode select pin. The PWM/SKIP pin is used to change the outputs operating mode. If this terminal is lower than 0.5 V, it works in PWM mode. When a minimum voltage of 2 V is applied, the device operates in skip mode. In light load condition ( 0.2 A), the skip mode gives a short pulse to the low-sid

40、e FETs instead of a full pulse. With this control, switching frequency is lowered and switching loss is reduced. Also, the output capacitor energy discharging through the output inductor and low-side FETs is stopped. Therefore, this device achieves a higher efficiency in light load conditions. 5 CT

41、I/O External capacitor from CT to GND for adjusting the triangle oscillator. 6 5V_STBY I 5 V linear regulator control 7 GND Control GND. 8 REF O 0.85 V reference voltage output. The 0.85 V reference voltage is used for setting the output voltage and the voltage protection. This reference voltage is

42、dropped down from a 5 V regulator. 9 STBY1 I Standby control for CH1. SMPS1 can be switched into standby mode separately by grounding the STBY1 pin. 10 STBY2 I Standby control for CH2. SMPS2 can be switched into standby mode separately by grounding the STBY2 pin. 11 FLT I/O Fault latch timer pin. An

43、 external capacitor is connected between FLT and GND to set the FLT enable time up. 12 POWERGOOD O Power good open-drain output. When low, POWERGOOD reports an output fail condition. PG comparators monitor both SMPSs over voltage and UVLO of VREF5. The threshold is 7 %. When the SMPS starts up, the

44、POWERGOOD pins output goes high. POWERGOOD also monitors VREF5s UVLO output. 13 SOFTSTART2 I/O External capacitor from SOFTSTART2 to GND for CH2 softstart control. Separate soft-start terminals make it possible to set the start-up time of each output independently. 14 FB2 O Feedback output CH2 error

45、 amplifier. 15 INV2 I Inverting input of the CH2 error amplifier, skip comparator, and OVP2/UVP2. 16 LH2 I/O Bootstrap capacitor connection fro CH2 high side gate drive. 17 OUT2_u O Gate drive output for CH2 high side switching FETs. 18 LL2 I/O Bootstrap this pin low for CH2 high side gate driving r

46、eturn and output current protection. Connect this pin to the junction of the high side and low side FETs for a floating drive configuration. 19 OUT2_d O Gate drive output for CH2 low side gate drive. 20 OUTGND2 Ground for CH2 FET drivers. FIGURE 2. Terminal connections. Provided by IHSNot for Resale

47、No reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04645 REV B PAGE 10 Device type 01 Case outline X Terminal number Terminal symbol I/O Description 21 REG5V_IN I External 5 V input. 22 VREF5 O 5

48、 V internal regulator output. 23 TRIP2 I External resistor connection for CH2 output current control. 24 VCCSupply voltage input. 25 TRIP1 I External resistor connection for CH1 output current control. 26 OUTGND1 Ground for CH1 FET drivers. 27 OUT1_d O Gate drive output for CH1 low side gate drive. 28 LL1 I/O Bootstrap this pin low for C