DLA DSCC-VID-V62 04644 REV A-2010 MICROCIRCUIT DIGITAL CMOS 3 3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149 1 (JTAG) TAP TRANSCEIVERS MONOLITHIC SILICON.pdf
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1、 REVISIONSLTR DESCRIPTION DATE APPROVEDA Update boilerplate paragraphs to current requirements. - PHN 10-04-06 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PR
2、EPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.milOriginal date of drawing CHECKED BY Charles F. Saffle TITLE MICROCIRCUIT, DIGITAL, CMOS, 3.3-V 10-BIT ADDRESSABLE SCAN PORTS, MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS, MONO
3、LITHIC SILICON YY-MM-DD 04-01-29 APPROVED BY Thomas M. Hess SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04644 REV A PAGE 1 OF 13 AMSC N/A 5962-V040-10 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A
4、 CODE IDENT NO. 16236 DWG NO. V62/04644 REV A PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 3.3-V 10-bit addressable scan ports, multidrop-addressable IEEE Std 1149.1 (JTAG) TAP transceivers microcircuit, with an operating temperature range of -40C
5、to +85C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturers PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04644 - 01 X E Drawing Device type Case outline Lea
6、d finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device type Generic Circuit function 01 SN74LVT8996-EP 3.3-V 10-bit addressable scan ports, multidrop-addressable IEEE Std 1149.1 (JTAG) TAP transceivers 1.2.2 Case outline. The case outline are as specified herein. Outline le
7、tter Number of pins JEDEC PUB 95 Package style X 24 JEDEC MS-013 Plastic small-outline Y 24 JEDEC MO-153 Plastic small-outline 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Ti
8、n-lead plateC Gold plateD PalladiumE Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04644 REV A PAGE 3 1.3 Absolute maximum ratings.
9、1/ Supply voltage range (VCC) . -0.5 V to +4.6 V Input voltage range (VI) . -0.5 V to 7.0 V 2/ Voltage range applied to any output in the high or power-off state (VO) -0.5 V to 7.0 V 2/ Current into any output in the low state (IO) . 128 mA Current into any output in the high state (IO) . 64 mA 3/ I
10、nput clamp current (IIK) (VIVCC. 4/ The package thermal impedance is calculated in accordance with JESD 51-7. 5/ Use of this product beyond the manufacturers design rules or stated parameters is done at the users risk. The manufacturer and/or distributor maintain no responsibility or liability for p
11、roduct used beyond the stated limits. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04644 REV A PAGE 4 2. APPLICABLE DOCUMENTS JEDEC PUB 95 Registered and Standa
12、rd Outlines for Semiconductor Devices JEDEC STD 51-7 - High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Applications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org
13、) IEEE Standard 1149.1-1990 - Standard Test Access Port and Boundary Scan Architecture (Applications for copies should be addressed to the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, Piscataway, NJ 08855-1331) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly
14、marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applic
15、able) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specif
16、ied herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Block diagram. The block diagram shall be as shown in figure 2. 3.5.3 Terminal connections. The terminal connections shall be as shown in figure 3. 3.5.4 Timing waveforms. The timing wavefor
17、ms shall be as shown in figure 4. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04644 REV A PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbo
18、l Test conditions -40C TA +85C Device type: All unless otherwise specified VCCLimits Unit Min Max Input clamp voltage VIKII= -18 mA 2.7 V -1.2 V High level output voltage VOHIOH= -100 A 2.7 V and 3.6 V VCC 0.2 V IOH= -8 mA 2.7 V 2.4 IOH= -32 mA 3.0 V 2.0 Low level output voltage VOLIOL= 100 A 2.7 V
19、0.2 V IOL= 24 mA 0.5 IOL= 16 mA 3.0 V 0.4 IOL= 32 mA 0.5 IOL= 64 mA 0.55 Input current IIVI= 5.5 V 0.0 V and 3.6 V 10 A PTCK VI= VCCor GND 3.6 V 1.0 High level input current IIHPTDI, PTMS, PTRSTnullnullnullnullnullnullnullnullnullVI= VCC3.6 V 1.0 A A9 A0, BYPnullnullnullnullnull, STDI VI= VCC3.6 V 1
20、.0 Low level input current IILPTDI, PTMS, PTRSTnullnullnullnullnullnullnullnullnullVI= GND 3.6 V -8.0 -30 A A9 A0, BYPnullnullnullnullnull, STDI VI= GND 3.6 V -25 -100 Input/output power-off leakage current IoffVIor VO= 0.0 V to 4.5 V 0.0 V 100 A Three-state output leakage current high IOZHPTDO, STD
21、O VO= 3.0 V 3.6 V 5.0 A Three-state output leakage current low IOZLPTDO, STDO VO= 0.5 V 3.6 V -5.0 A Three-state output leakage current power-up IOZPUVO= 0.5 V to 3.0 V 0.0 V to 1.5 V 100 A Three-state output leakage current power-down IOZPDVO= 0.5 V to 3.0 V 0.0 V to 1.5 V 100 A Quiescent supply cu
22、rrent ICCOff, STCK = H, STMS = H IO= 0.0 A VI= VCCor GND 3.6 V 2.0 On, PTDO = L, STCK = L, STDO = L, STMS = L 20 On, PTDO = H, STCK = H, STDO = H, STMS = H 7.0 TRST, STCK = L 10 Quiescent supply current delta, TTL input levels ICC2/ One input at VCC 0.6 V. Other inputs at VCCor GND. 3.0 V and 3.6 V
23、0.2 mA Input capacitance CIVI= 3.0 V or 0.0 V, TA= 25C 3.3 V 3.5 TYP pF Output capacitance COVO= 3.0 V or 0.0 V, , TA= 25C 3.3 V 6.5 TYP See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS CO
24、LUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04644 REV A PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Test conditions -40C TA +85C Device type: All unless otherwise specified VCCLimits Unit Min Max Clock frequency fclockPTCK See figure 4 2.7 V 20 MHz 3.0
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