DLA DSCC-VID-V62 04603 REV D-2008 MICROCIRCUIT DIGITAL CMOS FLOATING-POINT DIGITAL SIGNAL PROCESSOR MONOLITHIC SILICON《单片硅浮点数字信号处理器CMOS数字微电路》.pdf

《DLA DSCC-VID-V62 04603 REV D-2008 MICROCIRCUIT DIGITAL CMOS FLOATING-POINT DIGITAL SIGNAL PROCESSOR MONOLITHIC SILICON《单片硅浮点数字信号处理器CMOS数字微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA DSCC-VID-V62 04603 REV D-2008 MICROCIRCUIT DIGITAL CMOS FLOATING-POINT DIGITAL SIGNAL PROCESSOR MONOLITHIC SILICON《单片硅浮点数字信号处理器CMOS数字微电路》.pdf（60页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Add device type 02. Update boilerplate to current MIL-PRF-38535 requirements. - CFS 04-10-22 Thomas M. Hess B Correct lead finishes on last page. - CFS 05-11-08 Thomas M. Hess C Add device type 03. - CFS 07-08-17 Thomas M. Hess D Add device type 04. - PHN 0

2、8-08-04 Thomas M. Hess Prepared in accordance with ASME Y14.24 Vendor item drawing REV D D D D D D D D D D D D D D D D D D D D D PAGE 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 REV D D D D D D D D D D D D D D D D D D D D D D PAGE 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

3、 35 36 37 38 39 REV D D D D D D D D D D D D D D D D D REV STATUS OF PAGES PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY Charles F. Saffle DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO 43218-3990 Original date of drawing CHECKED BY Charles F. Saffle APPROVED BY Thomas M. Hess T

4、ITLE MICROCIRCUIT, DIGITAL, CMOS, FLOATING-POINT DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON SIZE A CODE IDENT. NO. 16236 DWG NO. V62/04603 YY-MM-DD 04-02-04 REV D PAGE 1 OF 60 AMSC N/A 5962-V059-08 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DE

5、FENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04603 REV D PAGE 2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance Floating-Point Digital Signal Processor microcircuit, with an operating temperature range of -40C to +115C

6、 for device type 01, an operating temperature range of -40C to +105C for device type 02, an operating temperature range of -55C to +105C for device type 03, and an operating temperature range of -55C to +125C for device type 04. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer

7、s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/04603 - 01 X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) 1.2.1 Device type(s). Device

8、 type Generic Circuit function 01 SM320C6713-EP Floating-Point Digital Signal Processor 02 SM32C6713B-EP Floating-Point Digital Signal Processor 03 SM32C6713B-EP Floating-Point Digital Signal Processor 04 SM32C6713B-EP Floating-Point Digital Signal Processor 1.2.2 Case outline(s). The case outlines

9、are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 272 JEDEC MO-151 Plastic ball grid array 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator Material A Hot solder dip B Tin-

10、lead plate C Gold plate D Palladium E Gold flash palladium Z Other Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04603 REV D PAGE 3 1.3 Absolute maximum ratings.

11、 1/ Supply voltage range (CVDD). -0.3 V to +1.8 V 2/ Supply voltage range (DVDD). -0.3 V to +4.0 V 2/ Input voltage range (VI). -0.3 V to DVDD+ 0.5 V Output voltage range (VO) . -0.3 V to DVDD+ 0.5 V Operating case temperature range (TC): Device type 01. -40C to +115C 3/ Device type 02. -40C to +105

12、C 3/ Device type 03. -55C to +105C 3/ Device type 04. -55C to +125C 3/ Storage temperature range (TSTG). -65C to +150C 3/ 1.4 Recommended operating conditions. 4/ Supply voltage range, Core referenced to VSS(CVDD): Minimum (MIN) +1.2 V Nominal (NOM) +1.26 V Maximum (MAX) +1.32 V Supply voltage range

13、, I/O referenced to VSS(DVDD): Minimum (MIN) +3.13 V Nominal (NOM) +3.3 V Maximum (MAX) +3.47 V Maximum supply voltage difference CVDD - DVDD(VC-D) 1.32 V Maximum supply voltage difference DVDD - CVDD(VD-C) 2.75 V Minimum high level input voltage (VIH): All signals except CLKS1/SCL1, DR1/SDA1, SCL0,

14、 SDA0, and RESET +2.0 V CLKS1/SCL1, DR1/SDA1, SCL0,SDA0, and RESET +2.0 V Maximum low level input voltage (VIL): All signals except CLKS1/SCL1, DR1/SDA1, SCL0, SDA0, and RESET +0.8 V CLKS1/SCL1, DR1/SDA1, SCL0,SDA0, and RESET +0.3*DVDDV Maximum high level output current (IOH): 5/ Device type 01: All

15、 signals except ECLKOUT, CLKOUT2, CLKOUT3, CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 -8 mA ECLKOUT, CLKOUT2, and CLKOUT3 -16 mA Device types 02 and 03: All signals except ECLKOUT, CLKOUT2, CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 -8 mA ECLKOUT and CLKOUT2 -16 mA _ 1/ Stresses beyond those listed under “absol

16、ute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for exte

17、nded periods may affect device reliability. 2/ All voltage values are with respect to VSS. 3/ Long term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. 4/ The core supply should be powered up prior to (and pow

18、ered down after), the I/O supply. Systems should be designed to ensure that neither supply is powered up for an extended period of time if the other supply is below the proper operating voltage. 5/ Refers to dc (or steady state) currents only, actual switching currents are higher. Provided by IHSNot

19、 for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04603 REV D PAGE 4 1.4 Recommended operating conditions Continued. Maximum low level output current (IOL): 5/ Device type 01: All sig

20、nals except ECLKOUT, CLKOUT2, CLKOUT3, CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 +8 mA ECLKOUT, CLKOUT2, and CLKOUT3 +16 mA CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 . +3 mA Device types 02 and 03: All signals except ECLKOUT, CLKOUT2, CLKS1/SCL1, DR1/SDA1, SCL0, and SDA0 +8 mA ECLKOUT and CLKOUT2 +16 mA CLKS1

21、/SCL1, DR1/SDA1, SCL0, and SDA0 . +3 mA Operating case temperature range (TC): Device type 01. -40C to +115C Device type 02. -40C to +105C Device type 03. -55C to +105C Device type 04. -55C to +125C 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices (Ap

22、plications for copies should be addressed to the Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834 or online at http:/www.jedec.org) IEEE Standard 1149.1 - Standard Test Access Port and Boundary Scan Architecture (Applications for copies should be addressed to the Insti

23、tute of Electrical and Electronics Engineers, 445 Hoes Lane, Piscataway, NJ 08855-1331) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturers part number as shown in 6.3 herein and as follows: A. Manufacturers name, CAGE code, or logo B. Pin 1 identifier C

24、. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturers part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as

25、specified in 1.3, 1.4, and table I herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04603 REV D PAGE 5 3.4 Design, construction, and physical dimension. The

26、 design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Block diagram. The block diagram shall be as shown in figure 2. 3.5.3 Terminal connections. The terminal connections shall be as s

27、hown in figure 3. 3.5.4 Timing waveforms and test circuit. The timing waveforms and test circuit shall be as shown in figures 4a 4cc. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO.

28、 16236 DWG NO. V62/04603 REV D PAGE 6 TABLE I. Electrical performance characteristics. 1/ Limits Test Symbol Test conditions unless otherwise specified Device type Min Max Unit Electrical Characteristics 2/ High level output voltage VOH3/ IOH= MAX 4/ 2.4 V VOL3/ 0.4 Low level output voltage VOL5/ IO

29、L= MAX 4/ 0.4 V II3/ 170 Input current II5/ VI= VSSto DVDD10 A IOZ3/ 170 Off-state output current IOZ5/ VO= DVDDor 0.0 V 10 A Core supply current IDD2V6/ GDPS, CVDD= 1.26 V CPU clock = 200 MHz 560 TYP mA I/O supply current IDD3V6/ C6713, DVDD= 3.3 V EMIF speed = 100 MHz 75 TYP mA Input capacitance C

30、i7.0 pF Output capacitance CoAll 7.0 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04603 REV D PAGE 7 TABLE I. Electrical perfo

31、rmance characteristics - Continued. 1/ Limits Test Symbol Test conditions unless otherwise specified 2/ 7/ Device type Min Max Unit CLKIN Timing Requirements 8/ 9/ PLL MODE (PLLEN = 1) See ref. 1, figure 4b. 5.0 83.3 Cycle time, CLKIN tc(CLKIN)BYPASS MODE (PLLEN = 0) See ref. 1, figure 4b. 5.0 ns PL

32、L MODE (PLLEN = 1) See ref. 2, figure 4b. 0.4C Pulse duration, CLKIN high tw(CLKINH)BYPASS MODE (PLLEN = 0) See ref. 2, figure 4b. 0.4C ns PLL MODE (PLLEN = 1) See ref. 3, figure 4b. 0.4C Pulse duration, CLKIN low tw(CLKINL)BYPASS MODE (PLLEN = 0) See ref. 3, figure 4b. 0.4C ns PLL MODE (PLLEN = 1)

33、See ref. 4, figure 4b. 5.0 Transition time, CLKIN tt(CLKIN)BYPASS MODE (PLLEN = 0) See ref. 4, figure 4b. All 5.0 ns CLKOUT2 Switching Characteristics 10/ 11/ Cycle time, CLKOUT2 tc(CKO2)See ref. 1, figure 4c. C2 0.8 C2 + 0.8 ns Pulse duration, CLKOUT2 high tw(CKO2H)See ref. 2, figure 4c. (C2/2) 0.8

34、 (C2/2) + 0.8 ns Pulse duration, CLKOUT2 low tw(CKO2L)See ref. 3, figure 4c. (C2/2) 0.8 (C2/2) + 0.8 ns Transition time, CLKOUT2 tt(CKO2)See ref. 4, figure 4c. All 2.0 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-

35、DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04603 REV D PAGE 8 TABLE I. Electrical performance characteristics - Continued. 1/ Limits Test Symbol Test conditions unless otherwise specified 2/ 7/ Device type Min Max Unit CLKOUT3 Switching Characteristics 10/

36、 12/ 01 C3 0.6 C3 + 0.6 Cycle time, CLKOUT3 tc(CKO3)See ref. 1, figure 4d. 02, 03, 04 C3 0.9 C3 + 0.9 ns 01 (C3/2) 0.6 (C3/2) + 0.6 Pulse duration, CLKOUT3 high tw(CKO3H)See ref. 2, figure 4d. 02, 03, 04 (C3/2) 0.9 (C3/2) + 0.9 ns 01 (C3/2) 0.6 (C3/2) + 0.6 Pulse duration, CLKOUT3 low tw(CKO3L)See r

37、ef. 3, figure 4d. 02, 03, 04 (C3/2) 0.9 (C3/2) + 0.9 ns 01 2.0 Transition time, CLKOUT3 tt(CKO3)See ref. 4, figure 4d. 02, 03, 04 3.0 ns 01 1.5 6.5 Delay time, CLKIN high to CLKOUT3 valid td(CKINH-CKO3V)See ref. 5, figure 4d. 02, 03, 04 1.5 7.5 ns ECLKIN Timing Requirements 8/ Cycle time, ECLKIN tc(

38、EKI)See ref. 1, figure 4e. 10 ns Pulse duration, ECLKIN high tw(EKIH)See ref. 2, figure 4e. 4.5 ns Pulse duration, ECLKIN low tw(EKIL)See ref. 3, figure 4e. 4.5 ns Transition time, ECLKIN tt(EKI)See ref. 4, figure 4e. All 3.0 ns ECLKOUT Switching Characteristics 10/ 13/ 14/ Cycle time, ECLKOUT tc(EK

39、O)See ref. 1, figure 4f. E 0.9 E + 0.9 ns Pulse duration, ECLKOUT high tw(EKOH)See ref. 2, figure 4f. EH 0.9 EH + 0.9 ns Pulse duration, ECLKOUT low tw(EKOL)See ref. 3, figure 4f. EL 0.9 EL + 0.9 ns Transition time, ECLKOUT tt(EKO)See ref. 4, figure 4f. 2.0 ns Delay time, ECLKIN high to ECLKOUT high

40、 td(EKIH-EKOH)See ref. 5, figure 4f. 1.0 6.5 ns Delay time, ECLKIN low to ECLKOUT low td(EKIL-EKOL)See ref. 6, figure 4f. All 1.0 6.5 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE SUPPLY CENTER, COLUMBUS CO

41、LUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04603 REV D PAGE 9 TABLE I. Electrical performance characteristics - Continued. 1/ Limits Test Symbol Test conditions unless otherwise specified 2/ 7/ Device type Min Max Unit Asynchronous Memory Cycles Timing Requirements 15/ 16/ 17/ Setup time,

42、EDx valid before ARE high tsu(EDV-AREH)See ref. 3, figure 4g. 6.5 ns Hold time, EDx valid after ARE high th(AREH-EDV)See ref. 4, figure 4g. 1.0 ns Setup time, ARDY valid before ECLKOUT high tsu(ARDY-EKOH)See ref. 6, figure 4g. 3.0 ns Hold time, ARDY valid after ECLKOUT high th(EKOH-ARDY)See ref. 7,

43、figure 4g. All 2.3 ns Asynchronous Memory Cycles Switching Characteristics 16/ 17/ 18/ Output setup time, select signals valid to ARE low tosu(SELV-AREL)See ref. 1, figure 4g. RS*E 1.7 ns Output hold time, ARE high to select signals invalid toh(AREH-SELIV)See ref. 2, figure 4g. RH*E 1.7 ns Delay tim

44、e, ECLKOUT high to ARE valid td(EKOH-AREV)See ref. 5, figure 4g. 1.5 7.0 ns Output setup time, select signals valid to AWE low tosu(SELV-AWEL)See ref. 8, figure 4g. WS*E 1.7 ns Output hold time, AWE high to select signals invalid toh(AWEH-SELIV)See ref. 9, figure 4g. WH*E 1.7 ns Delay time, ECLKOUT

45、high to AWE valid td(EKOH-AWEV)See ref. 10, figure 4g. 1.5 7.0 ns Output setup time, ED valid to AWE low tosu(EDV-AWEL)See ref. 11, figure 4g. All (WS 1)*E 1.7 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DEFENSE

46、SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 DWG NO. V62/04603 REV D PAGE 10 TABLE I. Electrical performance characteristics - Continued. 1/ Limits Test Symbol Test conditions unless otherwise specified 2/ 7/ Device type Min Max Unit Synchronous-burst SRAM Cycles Timing Require

47、ments 19/ Setup time, read EDx valid before ECLKOUT high tsu(EDV-EKOH)See ref. 6, figure 4h. 1.5 ns Hold time, read EDx valid after ECLKOUT high th(EKOH-EDV)See ref. 7, figure 4h. All 2.5 ns Synchronous-burst SRAM Cycles Switching Characteristics 19/ 20/ Delay time, ECLKOUT high to CEx valid td(EKOH

48、-CEV)See ref. 1, figure 4h. 1.2 7.0 ns Delay time, ECLKOUT high to BEx valid td(EKOH-BEV)See ref. 2, figure 4h. 7.0 ns Delay time, ECLKOUT high to BEx invalid td(EKOH-BEIV)See ref. 3, figure 4h. 1.2 ns Delay time, ECLKOUT high to EAx valid td(EKOH-EAV)See ref.4, figure 4h. 7.0 ns Delay time, ECLKOUT high to EAx invalid td(EKOH-EAIV)See ref. 5, figure 4h. 1.2 ns Delay time, ECLKOUT high to ARE/SDCAS/SSADS