CEPT T CD 02-05 E-1986 Engineering Requirements for a Bus Interface to Be Used in Data Communication Equipment《要用于数据通信设备中的总线接口工程要求》.pdf

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1、CEPT T/CD*02-05*E Ab E 232b414 0003548 7 E Page E 1 Recommendation T/CD 02-05 (Odense 1986) ENGINEERING REQUIREMENTS FOR A BUS INTERFACE TO BE USED IN DATA COMMUNICATION EQUIPMENT Recommendation proposed by Working Group T/WG 10 ?Data communications? (CD) Text of the revised Recommendation adopted b

2、y the ?Telecommunications? Commission: ?The Conference of European Post and Telecommunications Administrations, considering - that working group CD has studied under the auspices of Question CD 1 the harmonization of Data Circuit Terminating Equipment, recommends - that the attached specification of

3、 engineering requirements for a bus interface to be used in data communication equipment as contained in Annex 1 to this Recommendation should be taken into account by all CEPT Administrations when the implementation of a relevant piece of equipment is being planned by Administrations.? Administrati

4、ons are free to stipulate additional requirements, and also which of the optional requirements, if any, are to be provided. Note 1. It should be noted that this Recommendation may be revised from time to time. Edition of April 15, 1987 CEPT T/CD*02-05* 8b H 232b4l.14 0003543 3 E T/CD 02-05 E Page 2

5、Annex 1 1. SCOPE This specification is generally applicable for use within data communication systems. Its application for specific equipment will be defined in relevant equipment specifications. These equipment specifications may also indicate which specific structures or options apply for that equ

6、ipment. 2. SYSTEM LAYOUT Three different structures are described in this specification. Selection of one of these structures is dependent on the application. - Structure I consists of one bus master unit connected to a number of bus slave units. - Structure II consists of a CENTRAL CONTROLLER conne

7、cted to a number of units, some or all of which have the capability of becoming bus master, under control of the CENTRAL CONTROLLER. - Structure III consists of a number of interconnected units, some or all of which have the capability of becoming bus master. Units negotiate this via a separate bus.

8、 Note. Units that do not have the capability to become bus master can be used in all three structures. 3. FUNCTIONAL CHARACTERISTICS The bus consists of a number of lines as listed in Table 1 (T/CD 02-05). Name Transfer control ADDRESS STROBE DATA STROBE WRITE INTERNAL ADDRESS STROBE DATAIADDRESS SO

9、URCE Master control BUS REQUEST STROBE BUS SEIZED BUS RELEASE PRIORITY Mairiterimice RESET HALT PERIPHERAL CONTROL SYSTEM CONTROL Dataladdress DATAIADDRESS ADDRESS Additionai - Abbr. AS DS WR IAS DAS BRS BS BR PR7-PRO RES HT PER SYS DA7-DAO A 15-A8 - Struct. Type TP/TS TP/TS TP/TS TP/TS oc TP/TS oc

10、TP oc TS TS - Status essential essential essential optional optional essential essential essential essential for further study for further study for further study for further study essential optional for further study Table 1 (T/CD 02-05). Bus lines. Note. For explanation of the column “type” refer

11、to section 5 of this specification. The ADDRESS STROBE line validates the signals on the DATA/ADDRESS lines DA7-DAO and poten- tially Al5.A8 as an address. The line is controlled by the bus master or by the CENTRAL CONTROLLER (structure 11). The DATA STROBE line validates the signals on the DATA/ADD

12、RESS lines as data. The line is controlled by the bus master or by the CENTRAL CONTROLLER (structure 11). Edition of April 15, 1987 4. 4.1. 4.1.1. 4.1.2. 4.1.3. - 1 CEPT T/CD*02-05*E 86 E 232bllLll 0003550 5 E T/CD 02-05 E Page 3 The WRITE line determines whether a transfer action is a read or a wri

13、te action. The line is controlled by the bus master or by the CENTRAL CONTROLLER (structure II). The INTERNAL ADDRESS STROBE line validates the signals on the DATA/ADDRESS lines as an internal address. The line is controlled by the bus master or by the CENTRAL CONTROLLER (struc- ture 11). The DATAIA

14、DDRESS SOURCE line is used to control repeaters in extended bus systems. The line is activated by the unit that activates the DATA/ADDRESS and/or ADDRESS lines. The BUS REQUEST STROBE line - in structure II validates the signals on the DATA/ADDRESS and ADDRESS fines as a bus request poll - in struct

15、ure III validates the signals on the PRIORITY and BUS SEIZED lines. This line is controlled The BUS SEIZED line - in structure II indicates that a unit has seized the bus and thus become bus master; - in structure III validates a bus request on the priority lines and initializes the transmit address

16、 procedure. The line is controlled by the master unit. The BUS RELEASE line indicates to a unit that it shall release the bus and thus cease to be the bus master, The line is controlled by the CENTRAL CONTROLLER (structure II). The PRIORITY lines detesmine which unit may become bus master. The line

17、is controlled by all units wishing to become bus master. The function of the RESET, HALT, PERIPHERAL CONTROL and SYSTEM CONTROL lines is under study. The DATAIADDRESS lines are multifunctional lines. Their function is determined by signals on STROBE lines. The ADDRESS lines contain the most signific

18、ant octet of an address when validated by the ADDRESS STROBE line. Additional lines may be defined for specific applications. Study is underway to detesmine whether some of these lines can be harmonized. address. The line is controlled by the CENTRAL CONTROLLER; by the master unit. BUS PROCEDURES Tr

19、ansfer Control The transfer control procedure is identical for all structures. Transfer actions consist of two or three different phases, the address phase, the optional internal address phase and the data phase. Address phase In this phase the bus master will apply a two octet address to the ADDRES

20、S lines (most significant octet) and the DATAIADDRESS lines (least significant octet). The master unit or the CENTRAL CONTROL- LER will activate the ADDRESS STROBE line. A unit responding to the address will enter the read/write active mode. Systems, not requiring more than 256 different addresses,

21、will not implement the optional ADDRESS lines. Internal address phase In this optional phase, the bus master will apply the internal address to the DATA/ADDRESS lines. The master unit or the CENTRAL CONTROLLER will activate the INTERNAL ADDRESS STROBE. The unit being in the read/write active mode wi

22、ll accept the internal address and regard subsequent data transfer actions as pertinent to this internal address. Theinternal address could, e,g. indicate a modem on a multiple modem unit or a timeslot in a multiplexer unit, etc. Data phase The procedure during this phase depends on whether the acti

23、on is a read or a write action, Edition of April 15, 1987 CEPT T/CD*02-05*E 6 E 2326434 0003553 7 I T/CD 02-05 E Page 4 4.1.3.1. 4.1.3.2. 4.1.4. 4.2, 4.2.1. 4,2,1,1, 4.2.1.2. 4.2.2. 4.2.2.1. Read action During a read action the master unit or the CENTRAL CONTROLLER will activate the DATA STROBE line

24、. The master unit will not activate the write line. The unit(s) being in the read/write active mode will apply a data octet to the DATA/ADDRESS lines. Write action During a write action the master unit or the CENTRAL CONTROLLER will activate the DATA STROBE line. The master unit will activate the wr

25、ite line and apply a data octet to the DATA/ADDRESS lines. The unit(s) being in the read/write active mode will receive the data octet. Detailed procediire The sequence of address, internal address and data phases is defined as follows: A complete sequence consists of one or more address phases foll

26、owed by one or more secundary phases. A secundary phase consists of zero or more internal address phases followed by one or more data phases. Units will leave the read/write active mode at the end of a complete sequence; .e. when a data phase is followed by an address phase. Internal addresses are r

27、eleased at the end of a secundary phase; i.e. when a data phase is followed by an internal address phase. Also a bus release action (structure 11) or a new request (structure III) may cause units to leave the read/write active mode. Master control Master control for structure II The following action

28、s are specified: - Bus grant action. - Bus release action. BUS grant action The CENTRAL CONTROLLER will apply the address of a unit to the DATA/ADDRESS and ADDRESS lines and activate the BUS REQUEST STROBE line. The unit, recognizing its address will, when it wishes to become bus master, respond by

29、activating the BUS SEIZED line. As long as this line remains activated, the unit is bus master. Systems, not requiring more than 256 different addresses, will not implement the optional ADDRESS lines. Bus release action Units may cease to be bus master in one of the following ways: - de-activation o

30、f the BUS SEIZED line by the unit; - activation of the BUS RELEASE line by the CENTRAL CONTROLLER. Master control for structure III Note I. Only units having an address equal to or less than 255 can become bus master in this structure. Note 2. Specific precautions may be required for start-up condit

31、ions. Bus grant negotiation takes place on a separate set of lines (BUS REQUEST STROBE, BUS SEIZED and PRIORITY) simultaneously with transfer actions on other lines. The action is divided into two phases: 1. to detect the level of priority defined by each unit on its own; 2. to choose a unit between

32、 all units with the same level of priority. Priority determination Each unit wishing to become bus master sends its level of priority on one of the PRIORITY lines while activating the BRS and BS lines. A unit detecting a higher priority on the lines than its own will withdraw. After some time only t

33、hose units having the highest priority will remain active. The way in which units determine their level or priority is not specified. Priority may depend on: - the message priority; - the message type; - the duration since the last message was sent, etc. Edition of April 15, 1987 CEPT T/CD*02-05*E 6

34、 2326434 0003552 9 4.2.2.2. 4.3. 5. 5.1. 5.2. 5.3. 5.4. O T/CD 02-05 E Page 5 Address determination In this phase only those units participate that have the highest priority. During this phase units will send their address on the PRIORITY lines. The procedure is then identical with that in the previ

35、ous phase (only the BRS line is used). The unit address is defined by 8 bits. Each unit will translate its address in three codes: - one for the most significant two bits; - one for the following three bits; - one for the least significant three bits. The decimal value of the three groups of bits (0

36、-7) will correspond to the decimal designation order of one of the PRO-PR7 lines. Each unit sends the rst code and withdraws if necessary. The same procedure is applied for all three codes. So, after 4 clock cycles on BRS, the new master is appointed. Optionally, each unit is able to detect the new

37、master, but for more reliability, the previous master will send the address of the new master on the DATA/ADDRESS and/or ADDRESS lines validated by a BUS REQUEST STROBE. Options Not all units present in a system wiil necessarily be capable of performing all actions described in this section. Dependi

38、ng on the application units may, e.g. implement or not implement the following capabili- ties : - become the bus master; - write as a bus master; - read as a bus master; - go into the readlwrite active mode; - write action in the read/write active mode; - read action in the read/write active mode. E

39、LECTRICAL CHARACTERISTICS In this section only the receiver characteristics are described in detail. Driver characteristics will depend on - the number of receivers to be driven; - the transfer rate; - the presence of bus terminations. Drivers Drivers may be of the following type - Totem-pole (TP) -

40、 Open collector (OC) - Three state (TS) Which type is applicable for which line is indicated in Table 1 (T/CD 02-05). The following characteristics apply - high level output current - low level output current - output capacitance Cout Receivers Receivers shall meet the following characteristics: - L

41、ow level input current - High level input current - Threshold voltage - Input capacitance -50 pA at Vo = 0.6 V three state off; -400 pA at Vi = 0.5 V 50 pA at Vi = 2.7 V 0.8 V Vt 2.0 V Cin 7 pF Transceivers Transceivers shall meet requirements of drivers and receivers. The total load capacitance, ho

42、wever, is limited to 18 pF. Repeaters As the fan-out of drivers is limited, repeaters are required in larger bus-systems. To minimize delay, a set-up as given in Figure 1 (T/CD 02-05) is recommended. Edition of April 15, 1987 CEPT T/CD*02-05*E 8b 2326434 0003553 O W T/CD 02-05 E Page 6 The direction

43、 in which the DATA/ADDRESS and ADDRESS lines are repeatered is determined by the DATA/ADDRESS SOURCE line. This line itself will not be repeatered. Note. Repeater Set-ups for structure III require further study. The electrical characteristics of the bus between the CENTRAL CONTROLLER (if present) an

44、d the repeaters is for further study. Study in CCITT Study Group XVII concerning a multipoint version of Recommendation V. 11 (“V. 12”) is to be considered. 6. BUS TIMING To ensure proper operation of a bus system based on this specification, the following general rules should be observed. All the c

45、ontrol lines are in the logical “1” condition when not activated. When a STROBE line moves to the logical “O” condition (active state), the unit which is responsible for the DATA/ADDRESS and ADDRESS lines during this phase can activate these lines. When after a certain time the control line moves ba

46、ck to the logical “1” conditions, the information on the DATA/ADDRESS and ADDRESS lines has to be valid. Note. It should be noted that in larger systems there will be a delay (propagation delay and delay due to repeaters) between the instant in which a unit activates a line and the instant in which

47、all other units in the system recognize this change in condition. This should be taken into account when designing systems and system components. The reaction times and thus the minimum required duration of the active states of the control lines are for the time being not specified. Further study is

48、 required to determine whether such times are to be specified, and if so, whether a unique value for all applications is to be preferred or that several classes of equipment, each with their own requirements should be introduced. Figures 2 (T/CD 02-05) - 8 (T/CD 02-05) show the basic timing arrangem

49、ents for: - an address phase; - an internal address phase; - a read action; - a write action; - a bus grant action (structure 11); - a bus release action; unit initiative (structure 11); - a bus release action; CENTRAL CONTROLLER initiative (structure 11). Timing arrangements for structure III are to be defined. 7, MECHANICAL CHARACTERISTICS The physical dimensions of a unit are those specified for type II or III cards in the draft CEPT specification of equipment practice for Data Transmission Equipment (T/CD O 1-14), the latter type being under study. The connector and its position are