BS IEC 796-1-1991 Microprocessor system bus - 8-bit and 16-bit data MULTIBUS I Functional description with electrical and timing specifications《微处理器系统总线 8位和16位数据多路总线I 第1部分 电气和定时规范功.pdf

《BS IEC 796-1-1991 Microprocessor system bus - 8-bit and 16-bit data MULTIBUS I Functional description with electrical and timing specifications《微处理器系统总线 8位和16位数据多路总线I 第1部分 电气和定时规范功.pdf》由会员分享，可在线阅读，更多相关《BS IEC 796-1-1991 Microprocessor system bus - 8-bit and 16-bit data MULTIBUS I Functional description with electrical and timing specifications《微处理器系统总线 8位和16位数据多路总线I 第1部分 电气和定时规范功.pdf（48页珍藏版）》请在麦多课文档分享上搜索。

1、BRITISH STANDARD BS IEC 796-1:1990 Implementation of IEC 796-1:1990 Microprocessor systembus 8-bit and 16-bit Data (MULTIBUS I) Part 1: Functional description with electrical and timing specificationsBSIEC796-1:1990 This British Standard, having been prepared under thedirectionof the InformationSyst

2、ems TechnologyStandards Policy Committee, was published underthe authority of the Standards Board and comes into effect on 28February1991 BSI 04-2000 The following BSI references relate to the work on this standard: Committee reference IST/6 Draft for comment 90/67535 DC ISBN 0 580 19346 2 Committee

3、s responsible for this British Standard The preparation of this British Standard was entrusted by the Information Systems Technology Standards Policy Committee (IST/-) to Technical Committee IST/6, upon which the following bodies were represented: Association for Payment Clearing Services British Co

4、mputer Society British Telecommunications plc Business Equipment and Information Technology Association Department of Trade and Industry (Information Technology Standards Unit) Department of Trade and Industry (National Physical Laboratory) Electricity Supply Industry in England and Wales Electronic

5、 Engineering Association HM Treasury (Central Computer and Telecommunications Agency) Information Technology Users Standards Association Institute of Data Processing Management Inter-Universities Computing Committee Joint Network Team National Computing Centre Ltd. National Health Service OFTEL (Off

6、ice of Telecommunications) Post Office Telecommunications Engineering and Manufacturing Association Telecommunications Managers Association Amendments issued since publication Amd. No. Date CommentsBSIEC796-1:1990 BSI 04-2000 i Contents Page Committees responsible Inside front cover National forewor

7、d ii Foreword v Text of IEC 796-1 1BSIEC796-1:1990 ii BSI 04-2000 National foreword This British Standard reproduces verbatim IEC796-1:1990and implements it as the UK national standard. This British Standard is published under the direction of the Information Systems Technology Standards Policy Comm

8、ittee whose Technical Committee IST/6has the responsibility to: aid enquirers to understand the text; present to the responsible international committee any enquiries on interpretation, or proposals for change, and keep UK interests informed; monitor related international and European developments a

9、nd promulgate them in the UK. For the purposes of this British Standard, any references to page numbers in the text should be ignored. NOTEInternational and European Standards, as well as overseas standards, are available from BSI Sales Department, BSI, Linford Wood, Milton Keynes, MK14 6LE. A Briti

10、sh Standard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. Summary of pages This document comprises a front

11、 cover, an inside front cover, pages i and ii, theIEC title page, pages ii to vi, pages 1to 37 and a back cover. This standard has been updated (see copyright date) and may have had amendments incorporated. This will be indicated in the amendment table on the inside front cover.BSIEC796-1:1990 ii BS

12、I 04-2000 Contents Page Foreword v Preface v Introduction 1 Section 1. General 1.1 Scope 1 1.2 Object 1 1.3 Definitions 2 1.3.1 General System Terms 2 1.3.1.1 Compatibility (IEC Publication 625-1) 2 1.3.1.2 Bus Cycle 2 1.3.1.3 Interface (IEC Publication 625-1) 2 1.3.1.4 Interface System (IEC Publica

13、tion 625-1) 2 1.3.1.5 Override 2 1.3.1.6 System 2 1.3.2 Signals and Paths (IEC Publication 625-1) 2 1.3.2.1 Bus (IEC Publication 625-1) 2 1.3.2.2 Byte 2 1.3.2.3 Word 2 1.3.2.4 Signal (IEC Publication 625-1) 2 1.3.2.5 Signal Parameter (IEC Publication 625-1) 2 1.3.2.6 Signal Level (IEC Publication 62

14、5-1) 3 1.3.2.7 High State (IEC Publication 625-1) 3 1.3.2.8 Low State (IEC Publication 625-1) 3 1.3.2.9 Signal Line (IEC Publication 625-1) 3 1.3.2.10 Master 3 1.3.2.11 Slave 3 Section 2. Functional specifications 2.1 Bus Elements 3 2.1.1 Masters 3 2.1.2 Slaves 4 2.1.3 Bus Signals 4 2.1.3.1 Control

15、Lines 5 2.1.3.1.1 Clock Lines 5 2.1.3.1.2 Command Lines (MWTC*, MRDC*, IOWC*, IORC*) 5 2.1.3.1.3 Transfer Acknowledge Line (XACK*) 5 2.1.3.1.4 Initialize (INIT*) 5 2.1.3.1.5 Lock (LOCK*) 5 2.1.3.2 Address and Inhibit Lines 6 2.1.3.2.1 Address Lines (24 lines) 6 2.1.3.2.2 Byte High Enable Line (BHEN*

16、) 6 2.1.3.2.3 Inhibit Lines (INH1* and INH2*) 6 2.1.3.3 Data Lines (D0* D15*) 6 2.1.3.4 Interrupt Lines 6 2.1.3.4.1 Interrupt Request Lines (INT0* INT7*) 6 2.1.3.4.2 Interrupt Acknowledge (INTA*) 6 2.1.3.5 Bus Exchange Lines 7 2.1.3.5.1 Bus Request (BREQ*) 7 2.1.3.5.2 Bus Priority (BPRN* and BPRO*)

17、7 2.1.3.5.3 Bus Busy (BUSY*) 7 2.1.3.5.4 Common Bus Request (CBRQ*) 7BSIEC796-1:1990 BSI 04-2000 iii Page 2.2 Data Transfer Operation 7 2.2.1 Data Transfer Overview 8 2.2.2 Signal Descriptions 9 2.2.2.1 Initialize (INIT*) 9 2.2.2.2 Constant Clock (CCLK*) 9 2.2.2.3 Address Lines (A0* A23*) 9 2.2.2.4

18、Data Lines (D0* D15*) 10 2.2.2.5 Bus Commands 12 2.2.2.5.1 Read Operation 12 2.2.2.5.2 Write Operation 13 2.2.2.5.3 Transfer Acknowledge (XACK*) 13 2.2.2.5.4 Inhibit (INH1* and INH2*) 14 2.2.2.6 Lock (LOCK*) 16 2.3 Interrupt Operations 16 2.3.1 Interrupt Signal Lines 16 2.3.1.1 Interrupt Request Lin

19、es (INT0* INT7*) 16 2.3.1.2 Interrupt Acknowledge (INTA*) 17 2.3.2 Classes of Interrupt Implementation 17 2.3.2.1 Non-Bus Vectored Interrupts 17 2.3.2.2 Bus Vectored Interrupts 17 2.4 Bus Exchange 18 2.4.1 Bus Exchange Signals 18 2.4.1.1 Bus Clock (BCLK*) 19 2.4.1.2 Bus Busy (BUSY*) 19 2.4.1.3 Bus P

20、riority IN (BPRN*) 19 2.4.1.4 Bus Priority OUT (BPRO*) 20 2.4.1.5 Bus Request (BREQ*) 20 2.4.1.6 Common Bus Request (CBRQ*) (Optional) 20 2.4.2 Bus Exchange Priority Techniques 20 2.4.2.1 Serial Priority Technique 20 2.4.2.2 Parallel Arbitration Technique 21 Section 3. Electrical specifications 3.1

21、General Bus Considerations 22 3.1.1 Logical and Electrical State Relationships 22 3.1.2 Signal Line Characteristics 22 3.1.2.1 In-Use Signal Line Requirements 22 3.1.2.2 Backplane Signal Trace Characteristics 23 3.1.3 Power Supply Specification 23 3.1.4 Temperature and Humidity 25 3.2 Timing 25 3.2.

22、1 Read Operations (I/O and Memory) 26 3.2.2 Write Operations (I/O and Memory) 27 3.2.3 Inhibit Operations 28 3.2.4 Interrupt Implementations 28 3.2.4.1 NBV Interrupts 28 3.2.4.2 BV Interrupts 28 3.2.5 Bus Control Exchanges 29 3.2.5.1 Serial Priority 30 3.2.5.2 Parallel Priority 31BSIEC796-1:1990 iv

23、BSI 04-2000 Page 3.2.6 Miscellaneous Timing 31 3.3 Receivers, Drivers and Terminations 31 Section 4. Levels of compliance 4.1 Variable Elements of Capability 36 4.1.1 Data Path 36 4.1.2 Memory Address Path 36 4.1.3 I/O Address Path 36 4.1.4 Interrupt Attributes 36 4.2 Masters and Slaves 37 4.3 Compl

24、iance Level Notation 37 4.3.1 Data Path 37 4.3.2 Memory Address Path 37 4.3.3 I/O Address Path 37 4.3.4 Interrupt Attributes 37 4.3.5 Example 37 4.3.6 Compliance Marking 37 Figure 1 Bus master and slave example 4 Figure 2 Bus Interface Lines 8 Figure 3 Bus read operation 9 Figure 4 Bus write operati

25、on 9 Figure 5 Bus address line usage 10 Figure 6 Bus data line usage 11 Figure 7 Memory or I/O read timing 12 Figure 8 Memory or I/O write timing 13 Figure 9 Inhibit timing for write operation 15 Figure 10 Bus lock usage 16 Figure 11 Lock timing 17 Figure 12 Non-bus vectored (NBV) interrupt logic 18

26、 Figure 13 Bus vectored (BV) interrupt logic 19 Figure 14 Serial priority technique 21 Figure 15 Parallel priority technique 21 Figure 16 Setup, hold and command ringing summary 23 Figure 17 Line-to-line coupling characteristics 24 Figure 18 Read AC timing 27 Figure 19 Write AC timing 27 Figure 20 I

27、nhibit AC timing 28 Figure 21 Bus vectored (BV) interrupt AC timing 29 Figure 22 Bus exchange AC timing 30 Figure 23 Common bus request AC timing 30 Figure 24 Serial priority AC timing 31 Figure 25 Parallel priority AC timing 32 Figure 26 Constant clock AC timing 32 Figure 27 Command separation AC t

28、iming 33 Figure 28 Initialize AC timing 33 Figure 29 Lock AC timing 33 Table I Power Supply Specifications 24 Table II System Bus Timing Specifications Summary 25 Table III Bus drivers, receivers and terminations 34BSIEC796-1:1990 BSI 04-2000 v Foreword 1) The formal decisions or agreements of the I

29、EC on technical matters, prepared by Technical Committees on which all the National Committees having a special interest therein are represented, express, as nearly as possible, an international consensus of opinion on the subjects dealt with. 2) They have the form of recommendations for internation

30、al use and they are accepted by the National Committees in that sense. 3) In order to promote international unification, the IEC expresses the wish that all National Committees should adopt the text of the IEC recommendation for their national rules in so far as national conditions will permit. Any

31、divergence between the IEC recommendation and the corresponding national rules should, as far as possible, be clearly indicated in the latter. 4) The IEC has not laid down any procedure concerning marking as an indication of approval and has no responsibility when an item of equipment is declared to

32、 comply with one of its recommendations. Preface This standard has been prepared by Sub-Committee47B 1) : Microprocessor Systems, of IEC Technical Committee No. 47: Semiconductor Devices. This standard forms Part1of a series of publications, the other parts being: The text of this standard is based

33、upon the following documents: Full information on the voting for the approval of this standard can be found in the Voting Report indicated in the above table. The following IEC publication is quoted in this standard: 1) IEC Sub-Committee 47B has now been transferred to ISO/IEC JTC1. This standard wa

34、s approved according to IEC procedures and is therefore published as an IEC standard. Publication796-2:1990: Microprocessor system bus 8-bit and16-bit data (MULTIBUS I) Part2: Mechanical and pin descriptions for the system bus configuration, with edge connectors (direct). Publication796-3:1990: Part

35、3: Mechanical and pin descriptions for the Eurocard configuration with pin and socket (indirect) connectors. Six Months Rule Report on Voting 47B(C0)8 47B(C0)14 Publication No. 625-1:1979: An interface system for programmable measuring instruments (byte serial, bit parallel), Part1: Functional speci

36、fications, electrical specifications, mechanical specifications, system applications and requirements for the designer and user.vi blankBSIEC796-1:1990 BSI 04-2000 1 Introduction This standard is one of a series which deals with the electrical and mechanical interfaces to allow various microprocesso

37、r system components to interact with each other. The interface bus serves as a parallel transfer and utility signal interconnect for closely coupled system components. The series consists of one functional description and two alternative mechanical standards. Section 1. General 1.1 Scope This standa

38、rd is applicable to interface system components, for use in interconnecting data processing, data storage, and peripheral control devices in a closely coupled configuration. This interface system contains the necessary signals to allow the various system components to interact with each other. It al

39、lows memory and Input/Output (I/O) data transfers, direct memory accesses, generation of interrupts, etc. This standard provides a detailed description of all the elements and features that make up the system bus. The bus supports two independent address spaces: memory and I/O. During memory cycles

40、the bus allows direct addressability of up to16megabytes using24-bit addressing. During I/O bus cycles, the bus allows addressing of up to64K I/O ports using16-bit addressing. Both memory and I/O cycles can support8-bit data transfers. The bus structure is built upon the master-slave concept where t

41、he master device in the system takes control of the bus and the slave device, upon decoding its address, acts upon the command provided by the master. This handshake (master-slave relationship) between the master and slave devices allows modules of different speeds to be interfaced via the bus. It a

42、lso allows data rates up to five million transfers per second (bytes or words) to take place across the bus. Another important feature of the bus is the ability to connect multiple master modules for multiprocessing configurations. The bus provides control signals for connecting multiple masters in

43、either a serial or parallel priority fashion. With either of these two arrangements, more than one master may share bus resources. This standard has been prepared for those users who intend to evaluate or design products that will be compatible with the system bus structure. To this end, the necessa

44、ry signal definitions and timing and electrical specifications have been covered in detail. This standard deals only with the interface characteristics of microcomputer devices and not with design specifications, performance requirements, and safety requirements of modules. Throughout this standard,

45、 the term “system” denotes the byte or word interface system that, in general, includes all the circuits, connectors, and control protocol to effect unambiguous data transfer between devices. The term “device” or “module” denotes any product connected to the interface system that communicates inform

46、ation via the bus, and that conforms to the interface system definition. 1.2 Object This standard is intended to: 1) define a general purpose microcomputer system bus; 2) specify the device-independent electrical and functional interface requirements that a module shall meet in order to interconnect

47、 and communicate unambiguously via the bus system; 3) specify the terminology and definitions related to the system; 4) enable the interconnection of independently manufactured devices into a single functional system; 5) permit products with a wide range of capabilities to be interconnected to the s

48、ystem simultaneously; 6) define a system with a minimum of restrictions on the performance characteristics of devices connected to the system.BSIEC796-1:1990 2 BSI 04-2000 1.3 Definitions The following general definitions apply for the purpose of this standard. More detailed definitions can be found

49、 in the relevant sub-clause. 1.3.1 General System Terms 1.3.1.1 compatibility (IEC Publication625-1) the degree to which devices may be interconnected and used, without modification, when designed as defined throughout this standard (e.g. mechanical, electrical, functional) 1.3.1.2 bus cycle the process whereby digital signals effect the transfer of data bytes or words across the interface by means of an interlocked sequence of control signals. “Interlocked” denotes a fixed sequence