BS IEC 60748-4-3-2007 Semiconductor devices - Integrated circuits - Interface integrated circuits - Dynamic criteria for analogue-digital converters (ADC)《半导体器件 集成电路 接口集成电路 模拟数字转换器.pdf

《BS IEC 60748-4-3-2007 Semiconductor devices - Integrated circuits - Interface integrated circuits - Dynamic criteria for analogue-digital converters (ADC)《半导体器件 集成电路 接口集成电路 模拟数字转换器.pdf》由会员分享，可在线阅读，更多相关《BS IEC 60748-4-3-2007 Semiconductor devices - Integrated circuits - Interface integrated circuits - Dynamic criteria for analogue-digital converters (ADC)《半导体器件 集成电路 接口集成电路 模拟数字转换器.pdf（38页珍藏版）》请在麦多课文档分享上搜索。

1、 g49g50g3g38g50g51g60g44g49g42g3g58g44g55g43g50g56g55g3g37g54g44g3g51g40g53g48g44g54g54g44g50g49g3g40g59g38g40g51g55g3g36g54g3g51g40g53g48g44g55g55g40g39g3g37g60g3g38g50g51g60g53g44g42g43g55g3g47g36g58Part 4-3: Interface integrated circuits Dynamic criteria for analogue-digital converters (ADC) ICS

2、31.200Semiconductor devices Integrated circuits BRITISH STANDARDBS IEC 60748-4-3:2006BS IEC 60748-4-3:2006This British Standard was published under the authority of the Standards Policy and Strategy Committee on 28 February 2007 BSI 2007ISBN 978 0 580 50183 8Amendments issued since publicationAmd. N

3、o. Date Commentscontract. Users are responsible for its correct application.Compliance with a British Standard cannot confer immunity from legal obligations.National forewordThis British Standard was published by BSI. It is the UK implementation of IEC 60748-4-3:2006.The UK participation in its prep

4、aration was entrusted to Technical Committee EPL/47, Semiconductors.A list of organizations represented on EPL/47 can be obtained on request to its secretary.This publication does not purport to include all the necessary provisions of a INTERNATIONAL STANDARD IEC60748-4-3First edition2006-08Semicond

5、uctor devices Integrated circuits Part 4-3: Interface integrated circuits Dynamic criteria for analogue-digital converters (ADC) Reference number IEC 60748-4-3:2006(E) BS IEC 60748-4-3:2006CONTENTS INTRODUCTION.3 1 Scope.4 2 Normative references .4 3 Terms and definitions .4 4 Characteristics .5 5 M

6、easuring methods 7 5.1 Dynamic testing with sinusoidal signals.7 5.2 Dynamic tests with wideband signals.20 5.3 Linearity error of a linear ADC (EL) (EL(adj) (ET)22 5.4 Differential linearity error (ED) .28 Annex A (informative) Mathematical derivations.30 Annex B (informative) Wideband signal gener

7、ation and analysis.33 Bibliography34 Figure 1 Test arrangement for measurements on ADCs under dynamic conditions.7 Figure 2 Test arrangement for measurements on ADCs, using wideband signals .20 Figure 3 Record size versus total noise, for various numbers of records, ramp waveform input .23 Figure 4

8、Record size versus total noise, for various numbers of records, sine wave input 26 Table 1 Confidence level versus range of variable (in standard deviations)10 BS IEC 60748-4-3:2006 2 INTRODUCTION The use of ADCs has increased significantly in the last few years with the large increase in the use of

9、 digital signal processing. The majority of the processing of analogue signals now takes place in the digital domain, and this requires high precision in the conversion of signals from the analogue to the digital form. Consequently, the characterization of ADCs is of great importance. IEC 60748-4 co

10、ntains measuring methods for ADCs in which the test conditions are either static or change very slowly. However, some of the characteristics of an ADC can change to some degree with the rate of change of the input signal, and there are other characteristics that cannot be measured except under dynam

11、ic conditions. Consequently, a set of dynamic tests is required in order to obtain the response of an ADC when operated under dynamic conditions. The output of a dynamic test consists of the set of output code values obtained during the test. This record, being the sequence in time of a set of value

12、s, gives information in the “time-domain”. The result of applying the Fourier Transform to the record is information that is in the “frequency domain”, and this contains the spectrum of the output over the range of frequencies of interest. In particular, distortion, noise and spurious output frequen

13、cies can then be evaluated. This International Standard introduces a set of dynamic methods, which are now coming into use in industry and which rely mostly on measurements made with sinusoidal input signals, and of which the results are suitable for analysis in the frequency domain. It also include

14、s a further dynamic method that uses a wide-band input signal. For the reasons explained below, industry has shown great interest in this particular method. Linearity errors of an ADC are dependent on the amplitude of the input signal and its rate of change. Not so well known is that linearity error

15、s also depend on the instantaneous amplitude distribution, i.e. amplitude probability density function (APDF) of the input signal. This source of error is usually a result of localized heating effects in the integrated circuit and is dependent on ADC architecture and internal circuit layout. Single-

16、frequency signals have an APDF concentrated at the extremes and therefore exaggerate the effect of errors at the ends of the input range compared to those nearer the centre. Conversely, a wide-band signal has an APDF concentrated more around the centre of the input range. A wide-band signal is much

17、closer to the typical input signal in the majority of ADC applications than a single-frequency signal. Therefore, measurements made with such a signal will give more realistic error estimates. A wide-band signal can be generated from a pseudo-random binary sequence. Although such a signal appears to

18、 be noisy, it contains only a set of defined frequencies and is therefore suitable for measuring errors. BS IEC 60748-4-3:2006 3 SEMICONDUCTOR DEVICES INTEGRATED CIRCUITS Part 4-3: Interface integrated circuits Dynamic criteria for analogue-digital converters (ADC) 1 Scope This part of IEC 60748 spe

19、cifies a set of measuring methods and requirements for testing ADCs under dynamic conditions, together with associated terminology and characteristics. 2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edi

20、tion cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies. IEC 60748-4:1997, Semiconductor devices Integrated circuits Part 4: Interface integrated circuits IEC 60268-10:1991, Sound system equipment Part 10: Peak programme level mete

21、rs 3 Terms and definitions For the purposes of this document, the following definitions, in addition to those found in Chapter II, Clause 2, Terms for category II of IEC 60748-4:1997, apply. 3.1 coherent sampling process in which the output record contains samples taken from an integral number of in

22、put cycles of a repetitive waveform NOTE In general, this process is limited to the case where the number of input cycles and the number of samples in the record have no common factors. 3.2 equivalent-time sampling coherent sampling in which consecutive samples of a repetitive waveform, acquired fro

23、m multiple repetitions of the waveform, are assembled and re-arranged to produce a single record of samples that represent a single repetition of the waveform NOTE This process is normally used only when the spectrum of the input waveform contains significant amounts of energy at frequencies above h

24、alf the sampling frequency. It has the result that each frequency in the input appears in the output divided by the number of repetitions. For each successive input cycle, the set of samples is delayed (or advanced) relative to the previous set by a fixed amount. 3.3 (code) transition value boundary

25、 between two adjacent steps 3.4 signal-to-noise-and-distortion ratio for a pure sine-wave input, ratio of the r.m.s. amplitude of the output signal at the input frequency to the r.m.s. amplitude of all other signals in the output BS IEC 60748-4-3:2006 4 3.5 (spurious-free) dynamic range for a pure s

26、ine-wave input, ratio of the r.m.s. amplitude of the output signal at the input frequency to the largest r.m.s. amplitude of the output at any other single frequency 3.6 effective number of bits Nefpractical limit of the resolution of an ADC due to inherent noise and errors 3.7 signal-dependent timi

27、ng error effect equivalent to the delay of the instant of sampling, in an ADC, that is proportional to the rate of change of input voltage NOTE This effect is caused by the inherent voltage-dependent non-linearity of circuit elements in semiconductors. 3.8 spurious frequency persistent sine wave in

28、the output that is not considered to be a harmonic of the input frequency 3.9 word error rate probability of an output code having an error not attributable to random noise or to offset, gain, and linearity errors 4 Characteristics The following characteristics shall be included as characteristics a

29、pplicable to ADCs and should be read with reference to Chapter III, Section 2, Category II, Clause 4 of IEC 60748-4:1997.BS IEC 60748-4-3:2006 5 Requirements Ref. Characteristic Conditions at 25 C unless specified otherwise Letter Symbol Notes Max. Min. 4.1 Settling time ttotX 4.2 Long-term settling

30、 error ELTX 4.3 Rise and fall times tr; tfX 4.4 Limiting rate of change of output (slew rate) Supply voltages Input step amplitude Specified levels for transition time Clock frequency, as appropriate Conditions at other terminals Tolerance for settling time (v/t)max, SR X 4.5 Overload recovery times

31、 4.5.1 Input overload recovery time, where appropriate torX 4.5.2 Differential-mode input overload recovery time, where appropriate tordX 4.5.3 Common-mode input overload recovery time, where appropriate Supply voltages Input signal frequency, as appropriate Input signal amplitude Overload signal am

32、plitude and duration Clock frequency, as appropriate Conditions at other terminals torcX 4.6 Differential gain, where appropriate AdifX 4.7 Differential phase, where appropriate Supply voltages Input signal frequency, as appropriate Input signal amplitude Clock frequency, as appropriate DC input lev

33、els Conditions at other terminals Desired accuracy difX 4.8 Total harmonic distortion THD X 4.9 Spurious-free dynamic range SFDR X 4.10 Signal-to-noise-and-distortion ratio SINAD X 4.11 Effective number of bits Nef X 4.12 Signal-to-noise ratio SNR X 4.13 Noise floor NF X 4.14 Signal-dependent timing

34、 error Supply voltages Input signal frequency, as appropriate Input signal amplitude Clock frequency, as appropriate Highest harmonic excluded from noise, if not 10th Conditions at other terminals ESDTX BS IEC 60748-4-3:2006 6 5 Measuring methods 5.1 Dynamic testing with sinusoidal signals The follo

35、wing methods are to be read with reference to Chapter IV, Section 3, Category II, Group I of IEC 60748-4:1997. All references below to IEC 60748-4:1997 apply to this clause. 5.1.1 Dynamic testing of ADCs General requirements 5.1.1.1 Purpose To specify the general requirements for measuring the chara

36、cteristics of an ADC under dynamic conditions. 5.1.1.2 Circuit diagram Sine wave generator(s) Ramp generator Clock generator Sum FilterFilterLatch/ demuxComputerADC under testDC voltage Frequency synthesizer Square wave generator Buffer memory IEC 1503/06 Figure 1 Test arrangement for measurements o

37、n ADCs under dynamic conditions Optional elements are shown in broken outline. 5.1.1.3 Circuit description and requirements Case a) sine wave input The input voltage generator shall provide an accurate sinusoidal waveform with adjustable and stable amplitude and frequency. Case b) step input The inp

38、ut voltage generator shall provide a stepped wave, usually a square wave, without droop, and with adjustable and stable levels, duty-cycle and periodicity. Case c) linear input ramp The input voltage generator shall provide an accurate linear rising and/or falling waveform with adjustable and stable

39、 amplitude, duty-cycle and periodicity. BS IEC 60748-4-3:2006 7 All cases: Precautions shall be taken to avoid coupling between the sampling clock and the input circuits, and between the output and input circuits, and the networks used to combine input signals shall be designed to minimize any stray

40、 reactive elements that could affect the bandwidth of applied signals. Noise at the input should be small compared with the output noise that is generated within the ADC, and preferably no larger in magnitude than the noise that results from the quantization process, i.e. significantly less than 1 L

41、SB in magnitude. When necessary, and normally only for sine waves, input noise can be reduced by passing the signal through a low-pass or band-pass filter. The latter may also be used to reduce any frequency instability in the signal. Any impurity in the signal waveform and instability in its freque

42、ncy should be low enough not to affect the accuracy of the measurements. Similarly, any instability in the frequency (jitter) of the clock signal should be equally low. Ideally, the input signal and the clock signal should be synchronized from a common source. The adjustment range of the input volta

43、ge should be such that, at its maximum excursion, the most positive and most negative peaks exceed the working range of the ADC, but do not exceed its limiting input voltages. Equipment shall be included for the adjustment of offset and gain points of adjustable converters. For some measurements, bo

44、th step and sinusoidal inputs are applied together to the ADC. The recording equipment should be capable of storing each output code obtained during the test duration. In cases where this is physically not possible, or accuracy is reduced in a long test duration due to frequency instability, then th

45、e test may be divided into a set of segments of equal length, where the record of each segment is analysed separately, provided that for each segment the phase of the input signal at its start is either randomly chosen or uniformly distributed within the range 02. For analysis of the histogram of th

46、e ADC output, the recording equipment shall count the number of occurrences of each individual output code value during the test. The test duration should be such that each output code value appears enough times to achieve the required accuracy (see Figures 3 and 4 and also Annex A) to determine a s

47、uitable number. For analysis of the spectrum of the ADC output, the recording equipment shall record the code value of each individual sample during the test. 5.1.1.4 Special precautions regarding accuracy Note the comments above regarding signal purity, frequency stability, and input noise. In orde

48、r that each test is carried out with coherent sampling, the duration of each segment of the test shall be set to an integral number of input cycles. However, the periodicity or frequency of the input waveform and that of the sampling clock shall not have a common factor, thus fi= fs J/M (1) where fi

49、 is the input frequency; fs is the sampling frequency; BS IEC 60748-4-3:2006 8 M is the number of samples in a test record; J is the number of input periods in a test record, an integer, the fraction J/M shall be irreducible. If the requirement for J to be an integer is not met, then the method of analysis will give large errors. Although there is a mathematical procedure that can extract reasonably accurate results when J is not an integer, its use is outside the scope of this standa